# US 10,503,851 B2 · CMOS-photonics co-design

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- Number: US 10,503,851 B2
- Document ID: US10503851B2
- Status: Granted
- Kind: B2
- Application number: 16/065,716
- Filed: 2016-01-22
- Published: 2019-01-17
- Granted: 2019-12-10
- Earliest claimed: 2016-01-22
- Assignees: Hewlett Packard Enterprise Development LP
- Applicants: Hewlett Packard Enterprise Development LP
- Inventors: Tsung-Ching Huang; Chin-Hui Chen; Marco Fiorentino; Raymond G. Beausoleil
- Web page: https://patentgrep.com/patent/US10503851B2

## CPC

- G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
- G06F 30/20: Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30)
- G06F 30/30: Circuit design
- G06F 30/36: Circuit design at the analogue level
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In example implementations, a method executed by a processor is provided. The method receives a simulated photonic data input based on a theoretical photonic design that meets a target specification. A complementary metal-oxide semiconductor (CMOS) circuit design is designed based on the simulated photonic data input using a pre-layout simulation. An experimental photonic data input based on a fabricated photonics device that meets the target specification is received. The CMOS circuit is designed based on the experimental photonic data input using a post-layout simulation. A physical circuit CMOS circuit design and a layout that includes detailed physical dimensions associated with the physical CMOS circuit design that is based on the pre-layout and the post-layout are transmitted to a CMOS foundry.

## Claims

### Claim 1

A co-design method, comprising:
receiving, by a processor, a simulated photonic data input based on a theoretical photonic design that meets a target specification;
designing, by the processor, a complementary metal-oxide semiconductor (CMOS) circuit design based on the simulated photonic data input using a pre-layout simulation;
receiving, by the processor, an experimental photonic data input based on a fabricated photonics device that meets the target specification;
designing, by the processor, the CMOS circuit design based on the experimental photonic data input using a post-layout simulation; and
providing, by the processor, a physical CMOS circuit design and a layout that includes detailed physical dimensions associated with the physical CMOS circuit design that is based on the pre-layout simulation and the post-layout simulation.

### Claim 2 (depends on 1)

The co-design method of claim 1, wherein the simulated photonic data and the experimental photonic data are received from a photonics foundry.

### Claim 3 (depends on 1)

The co-design method of claim 1, wherein the fabricated photonics device comprises optical modulators.

### Claim 4 (depends on 1)

The co-design method of claim 1, wherein the physical CMOS circuit design comprises a modulator driver.

### Claim 5 (depends on 1)

The co-design method of claim 1, wherein the experimental photonic data input includes optical test data under various driving conditions.

### Claim 6 (depends on 5)

The co-design method of claim 5, wherein the various driving conditions include pre-emphasis techniques.

### Claim 7

A co-design apparatus, comprising:
a memory comprising instructions;
a processor coupled to the memory, the processor to execute the instructions to:
receive a first input of simulated data of an optical modulator design that meets a target specification;
design a modulator driver based on the first input of simulated data of a photonic device using a pre-layout simulation;
receive a second input of experimental data of an optical modulator based on the optical modulator design;
design the modulator driver based on the second input using a post-layout simulation; and
provide a physical modulator driver design and a physical layout associated with the physical modulator driver design that is based on the pre-layout simulation and the post-layout simulation.

### Claim 8 (depends on 7)

The co-design apparatus of claim 7, wherein the simulated data and the experimental data are received from a photonics foundry.

### Claim 9 (depends on 7)

The co-design apparatus of claim 7, wherein the instructions to design the modulator driver is based on a third input from a complementary metal-oxide semiconductor (CMOS) process design kit (PDK) from a CMOS foundry.

### Claim 10 (depends on 7)

The co-design apparatus of claim 7, wherein the experimental data input includes optical test data under various driving conditions.

### Claim 11 (depends on 10)

The co-design apparatus of claim 10, wherein the various driving conditions include pre-emphasis techniques.

### Claim 12

A non-transitory computer-readable storage medium encoded with instructions executable by a co-design processor, the computer-readable storage medium comprising:
instructions to generate simulated photonic data based on a theoretical photonic design that meets a target specification;
instructions to transmit the simulated photonic data as a first input to a pre-layout simulation of a complementary metal-oxide semiconductor (CMOS) circuit at a CMOS foundry;
instructions to generate experimental photonic data based on testing of a fabricated photonic device that meets the target specification; and
instructions to transmit the experimental photonic data as a second input to a post-layout simulation of the CMOS circuit at the CMOS foundry, wherein a physical CMOS circuit design fabricated by the CMOS foundry is based on the pre-layout simulation and the post-layout simulation of the CMOS circuit.

### Claim 13 (depends on 12)

The non-transitory computer readable storage medium of claim 12, wherein an optimal design of the theoretical photonic design is based on a convergence of a plurality of parameters of the simulated photonic data and the experimental photonic data.

### Claim 14 (depends on 12)

The non-transitory computer readable storage medium of claim 12, wherein the experimental photonic data includes optical test data under various driving conditions.

### Claim 15 (depends on 14)

The non-transitory computer readable storage medium of claim 14, wherein the various driving conditions include pre-emphasis techniques.