# US 10,503,849 B2 · Circuit testing and manufacture using multiple timing libraries > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,849 B2 - Document ID: US10503849B2 - Status: Granted - Kind: B2 - Application number: 15/703,781 - Filed: 2017-09-13 - Published: 2018-06-21 - Granted: 2019-12-10 - Earliest claimed: 2016-12-15 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Ravi Babu Pittu; Chung-Hsing Wang; Sung-Yen Yeh; Li Chung Hsu - Web page: https://patentgrep.com/patent/US10503849B2 ## CPC - G06F 30/3312: Timing analysis - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 2119/12: Timing analysis or timing optimisation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method includes generating a first timing library for a first set of circuit elements for a first set of input parameters. Generating the first timing library includes determining device characteristics for each of the circuit elements in the first set of circuit elements and storing the determined device characteristics in a database. A second timing library is generated for a second set of circuit elements for a second set of input parameters. The second timing library is generated by using one or more of the determined device characteristics previously stored in the database. A circuit is formed on a substrate. The circuit includes at least one of the first set of circuit elements or the second set of circuit elements. ## Claims ### Claim 1 A method, comprising: generating a first timing library for a first set of circuit elements for a first set of input parameters, wherein generating the first timing library includes determining device characteristics for each of the circuit elements in the first set of circuit elements and storing the determined device characteristics in a database; generating a second timing library for a second set of circuit elements for a second set of input parameters, wherein the second timing library is generated by obtaining device characteristics previously stored in the database for a first subset of the second set of circuit elements and determining device characteristics for a second subset of the second set of circuit elements using one of an aging simulation or a stress simulation; and forming a circuit on a substrate, wherein the circuit includes at least one of the first set of circuit elements or the second set of circuit elements. ### Claim 2 (depends on 1) The method of claim 1, wherein generating the first timing library comprises performing a stress simulation of the first set of circuit elements, wherein the stress simulation determines the device characteristics for each of the circuit elements in the first set of circuit elements. ### Claim 3 (depends on 1) The method of claim 1, wherein generating the first timing library comprises performing an aging simulation of the first set of circuit elements based on the device characteristics for each of the circuit elements in the first set of circuit elements, and wherein the aging simulation generates performance data for the first set of circuit elements at the first set of input parameters. ### Claim 4 (depends on 1) The method of claim 1, wherein the aging simulation of at least a portion of the second subset of the second set of circuit elements is based at least in part on the device characteristics of the first set of circuit elements, and wherein the aging simulation generates performance data for the second set of circuit elements at the second set of input parameters. ### Claim 5 (depends on 1) The method of claim 1, wherein the stress simulation of the second subset of circuit elements in the second set of circuit elements determines device characteristics for each of the second subset of circuit elements. ### Claim 6 (depends on 1) The method of claim 1, wherein the device characteristics are selected from the group consisting of: active device electrical characteristic shifts, gate leakage fluctuation, electrical characteristic shifts due to aging effects, self-heating effect (SHE), bias-temperature instability (BTI), hot carrier injection (HCI), and time dependent gate oxide breakdown (TDDB). ### Claim 7 (depends on 1) The method of claim 1, wherein the first set of circuit elements and the second set of circuit elements are different. ### Claim 8 (depends on 1) The method of claim 1, wherein the first timing library and the second timing library are generated using one or more SPICE simulations. ### Claim 9 (depends on 1) The method of claim 1, wherein the first set of input parameters includes a first targeted expected life and the second set of input parameters includes a second targeted expected life. ### Claim 10 A method, comprising: generating a first set of device characteristics for a set of circuit elements using a first set of input parameters; generating a first timing library for the set of circuit elements for a first targeted expected life, wherein the first timing library is generated using the first set of device characteristics; generating a second set of device characteristic for a subset of the set of circuit elements, wherein the second set of device characteristics are generated using a second set of input parameters; generating a second timing library for the second set of circuit elements for a second targeted expected life, wherein the second timing library is generated using a subset of the first set of device characteristics and the second set of device characteristics; and forming a circuit on a substrate, wherein the circuit includes the set of circuit elements. ### Claim 11 (depends on 10) The method of claim 10, wherein generating the first set of device characteristics comprises performing a stress simulation of the set of circuit elements, and wherein the first set of input parameters includes at least one stress parameter. ### Claim 12 (depends on 11) The method of claim 11, wherein the at least one stress parameter includes power, voltage, and temperature (PVT) parameters or signal integration parameters. ### Claim 13 (depends on 10) The method of claim 10, wherein generating the first timing library comprises performing an aging simulation of the set of circuit elements over the first targeted expected life. ### Claim 14 (depends on 10) The method of claim 10, wherein generating the second timing library comprises performing an aging simulation of the set of circuit elements over the second targeted expected life. ### Claim 15 (depends on 10) The method of claim 10, wherein the subset of first device characteristics includes device characteristics for each circuit element in the set of circuit elements. ### Claim 16 (depends on 10) The method of claim 10, wherein the device characteristics are selected from the group consisting of: active device electrical characteristic shifts, gate leakage fluctuation, electrical characteristic shifts due to aging effects, self-heating effect (SHE), bias-temperature instability (BTI), hot carrier injection (HCI), and time dependent gate oxide breakdown (TDDB). ### Claim 17 A method, comprising: generating first device characteristics for a set of circuit elements in a circuit; generating second device characteristics for the set of circuit elements in the circuit; storing the device characteristics in a database; generating a first timing library using an aging model, a first subset of the circuit elements, and a first set of input parameters, wherein the first timing library is generated using the first device characteristics, and wherein the first timing library includes a first set of performance data for the set of circuit elements; generating a second timing library using the aging model, a second subset of the circuit elements, and a second set of input parameters, wherein the second timing library is generated using a subset of the first device characteristics and the second device characteristics, and wherein the second timing library includes a second set of performance data for the set of circuit elements; and forming the circuit on a substrate when the first set of performance data meets or exceeds a predetermined performance threshold. ### Claim 18 (depends on 17) The method of claim 17, comprising forming the circuit on the substrate when the second set of performance data meets or exceeds the predetermined performance threshold. ### Claim 19 (depends on 18) The method of claim 18, wherein the first set of input parameters includes a first targeted expected lifetime and the second set of input parameters includes a second set of input parameters. ### Claim 20 (depends on 17) The method of claim 17, wherein the first device characteristics are generated by a stress simulation configured to simulate power, voltage, and temperature (PVT) or signal integration of the set of circuit elements.