# US 10,503,848 B2 · Target capture and replay in emulation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,848 B2 - Document ID: US10503848B2 - Status: Granted - Kind: B2 - Application number: 15/669,283 - Filed: 2017-08-04 - Published: 2017-11-23 - Granted: 2019-12-10 - Earliest claimed: 2015-11-13 - Assignees: Mentor Graphics Corporation - Applicants: Mentor Graphics Corporation - Inventors: Krishnamurthy Suresh; Satish Kumar Agarwal; Sanjay Gupta; Charles W. Selvidge - Web page: https://patentgrep.com/patent/US10503848B2 ## CPC - G06F 30/331: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation - G06F 9/455: Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines - H04L 43/50: Testing arrangements - H04L 67/08: specially adapted for terminal emulation, e.g. Telnet - G06F 11/26: Functional testing - G06F 2115/10: Processors - G06F 2117/08: HW-SW co-design, e.g. HW-SW partitioning - H04L 67/75: Indicating network or usage conditions on the user display - H04L 69/28: Timers or timing mechanisms used in protocols - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract An emulation process is performed with an emulator coupled to one or more targets. During a part or a whole of the emulation process, input signals to the emulator from the one or more targets are being captured, streamed out of the emulator and stored in one or more processor-readable media. The part or the whole of the emulation process is then repeated with the emulator decoupled to the one or more targets. During the repeating, the input signals stored in the one or more processor-readable media are being streamed back to the emulator. The streaming in both of the capture and replay modes may be through interfaces designed for small packets of data and fast streaming speed. ## Claims ### Claim 1 A method comprising: performing, using an emulator that is coupled to one or more targets and that is associated with a clock for a circuit design under test by the emulator, a part of an emulation process; during the performing of the part of the emulation process: capturing one or more signals that are being communicated to the emulator from the one or more targets, communicating the one or more input signals out of the emulator, and storing the one or more input signals in one or more processor-readable media; decoupling the emulator from the one or more targets; repeating, after the decoupling, the part of the emulation process; and during the repeating of the part of the emulation process, communicating the one or more input signals to the emulator from the one or more processor-readable media. ### Claim 2 (depends on 1) The method recited in claim 1, wherein the one or more processor-readable media are in a workstation. ### Claim 3 (depends on 1) The method recited in claim 1, wherein communicating the one or more input signals out of the emulator is performed via one or more interfaces configured to process packets of data between 500 bits and 2000 bits at a streaming speed between 2 and 3 gigabits per second. ### Claim 4 (depends on 3) The method recited in claim 3, wherein communicating the one or more input signals to the emulator from the one or more processor-readable media is performed via the one or more interfaces. ### Claim 5 (depends on 1) The method recited in claim 1, wherein the one or more targets comprises a dynamic target. ### Claim 6 (depends on 1) The method recited in claim 1, further comprising: slowing the clock for the circuit design based on adaptive clock management during the repeating of the part of the emulation process. ### Claim 7 (depends on 6) The method recited in claim 6, further comprising: temporarily suspending or temporarily stopping the clock for the circuit design based on the adaptive clock management. ### Claim 8 (depends on 1) The method recited in claim 1, further comprising: during the performing of the part of the emulation process capturing one or more reference output signals, communicating, out of the emulator, the one or more reference output signals, and storing the one or more reference output signals in the one or more processor-readable media. ### Claim 9 (depends on 8) The method recited in claim 8, further comprising: comparing, during the repeating of the part of the emulation process, one or more output signals with the reference output signals. ### Claim 10 (depends on 1) The method recited in claim 1, further comprising: fetching, during the repeating of the part of the emulation process, data from the emulator while the clock for the circuit design is stopped. ### Claim 11 An emulator comprising: a clock for a circuit design under test by the emulator; and circuitry configured to perform a method comprising: performing, when the emulator is coupled to one or more targets, a part of an emulation process; during the performing of the part of the emulation process: capturing one or more input signals that are being communicated to the emulator from the one or more targets, communicating the one or more input signals out of the emulator, and causing the one or more input signals to be stored in one or more processor-readable media; decoupling the emulator from the one or more targets; repeating, after the decoupling, the part of the emulation; and during the repeating of the part of the emulation process, communicating the one or more input signals to the emulator from the one or more processor-readable media. ### Claim 12 (depends on 11) The emulator recited in claim 11, wherein the one or more processor-readable media are in a workstation in communication with the emulator. ### Claim 13 (depends on 11) The emulator recited in claim 11, wherein communicating the one or more input signals out of the emulator is performed via one or more interfaces to the workstation, the one or more interfaces being configured to process a packet of data between 500 bits and 2000 bits at a streaming speed between 2 and 3 gigabits per second. ### Claim 14 (depends on 13) The emulator recited in claim 13 the one or more input signals to the emulator from the one or more processor-readable media is performed via the one or more interfaces. ### Claim 15 A method comprising: performing, using an emulator that is coupled to one or more targets and that is associated with a clock for a circuit design under test by the emulator, a part of an emulation process; during the performing of the part of the emulation process: capturing one or more input signals that are being communicated to the emulator from the one or more targets, communicating, while the clock for the circuit design is stopped, the one or more input signals out of the emulator, and storing the one or more input signals in one or more processor-readable media; decoupling the emulator from the one or more targets; repeating, after the decoupling, the part of the emulation process; and during the repeating of the part of the emulation process, communicating, while the clock for the circuit design is stopped, the one or more input signals to the emulator from the one or more processor-readable media. ### Claim 16 (depends on 15) The method recited in claim 15, wherein communicating, while the clock for the circuit design is stopped, the one or more input signals out of the emulator is performed via one or more interfaces configured to process packets of data between 500 bits and 2000 bits and at a streaming speed between 2 and 3 gigabits per second. ### Claim 17 (depends on 15) The method recited in claim 15, wherein communicating, while the clock for the circuit design is stopped, the one or more input signals to the emulator from the one or more processor-readable media is performed via the one or more interfaces. ### Claim 18 (depends on 15) The method recited in claim 15, further comprising: stopping the clock for the circuit design based on adaptive clock management. ### Claim 19 (depends on 18) The method recited in claim 18, wherein stopping the clock for the circuit design is performed by temporarily suspending the clock for the circuit design based on the adaptive clock management. ### Claim 20 (depends on 15) The method recited in claim 15, further comprising: during the performing of the part of the emulation process capturing one or more reference output signals, communicating the one or more reference output signals out of the emulator, and storing the one or more reference output signals in the one or more processor-readable media; and during the repeating of the part of the emulation process, comparing one or more output signals with the one or more reference output signals.