# US 10,503,841 B2 · Integrated circuit buffering solutions considering sink delays > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,841 B2 - Document ID: US10503841B2 - Status: Granted - Kind: B2 - Application number: 16/423,242 - Filed: 2019-05-28 - Published: 2019-09-12 - Granted: 2019-12-10 - Earliest claimed: 2017-06-22 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Ying Zhou; Stephen T. Quay; Lakshmi N. Reddy; Gustavo E. Tellez; Gi-Joon Nam; Jiang Hu - Web page: https://patentgrep.com/patent/US10503841B2 ## CPC - G06F 30/3312: Timing analysis - G06F 30/00: Computer-aided design [CAD] - G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - G06F 30/394: Routing (G06F30/396 takes precedence) - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 2119/12: Timing analysis or timing optimisation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions. ## Claims ### Claim 1 A method for optimizing timing in a VLSI circuit comprising: determining a most critical delay and a sum of critical delays for each solution in a set of buffer solutions for the VLSI circuit; quantifying, for each solution, a relationship between the most critical delay and the sum of critical delays; comparing each solution's relationship to the relationship of each other solution in the set of solutions; identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions; and pruning the at least one solution from the set of solutions. ### Claim 2 (depends on 1) The method of claim 1, further comprising continuing to prune solutions from the set of solutions until a target number of solutions remains. ### Claim 3 (depends on 1) The method of claim 1, further comprising submitting at least one remaining solution to an integrated circuit design process. ### Claim 4 (depends on 1) The method of claim 1, further comprising displaying at least one solution remaining in the set of the solutions on a user interface. ### Claim 5 (depends on 1) The method of claim 1, wherein quantifying a relationship between the most critical delay and the sum of critical delays comprises calculating a p-norm of the sum of delays. ### Claim 6 (depends on 5) The method of claim 5, wherein a solution has a worse relationship between the most critical delay and the sum of critical delays when the solution's p-norm of the sum of delays comprises a higher value than a p-norm of the sum of delays of at least one other solution of the set of solutions. ### Claim 7 (depends on 5) The method of claim 5, wherein the set of solutions is created according to a set of design parameters; and wherein a solution has a worse relationship between the most critical delay and the sum of delays when the solution's relationship is associated with a value which deviates from the design parameters by a greater margin than a value associated with the relationship between the most critical delay and the sum of critical delays of at least one other solution of the set of solutions. ### Claim 8 (depends on 1) The method of claim 1, further comprising determining a load cap and a buffer cost for each solution of the set of solutions. ### Claim 9 (depends on 8) The method of claim 8, further comprising comparing each solution's load cap and buffer cost with the load cap and buffer cost of each other solution in the set of solutions, wherein each solution has a characterization and the characterization comprises the solution's load cap, buffer cost, and relationship between the most critical delay and the sum of critical delays; and wherein the identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution of the set of solutions to have a worse relationship than the other solutions in the set of solutions further comprises identifying, based on the comparing of each solution's load cap and buffer cost with the load cap and buffer cost of each other solution in the set of solutions, at least one solution of the set of solutions to have a worse characterization than the other solutions in the set of solutions. ### Claim 10 (depends on 9) The method of claim 9, wherein a solution has a worse characterization if the solution's load cap has a lower value and the solution's buffer cost has a higher value than a load cap and a buffer cost of at least one other solution of the set of solutions. ### Claim 11 (depends on 1) The method of claim 1, wherein the circuit comprises one or more nodes and the most critical delay for each solution is found by calculating the delay at each node and identifying the node with the largest delay. ### Claim 12 (depends on 1) The method of claim 1, wherein the circuit comprises a source and one or more sinks, and wherein the sum of critical delays for a solution is calculated using a measurement of each critical delay in the solution taken from the sink to the source. ### Claim 13 A system for optimizing timing in a VLSI circuit, the system comprising: a memory; and a processor communicatively coupled to the memory, wherein the processor is configured to perform a method comprising: determining a most critical delay and a sum of critical delays for each solution in a set of buffer solutions for the VLSI circuit; quantifying, for each solution, a relationship between the most critical delay and the sum of critical delays; comparing each solution's relationship to the relationship of each other solution in the set of solutions; identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions; and pruning the at least one solution from the set of solutions. ### Claim 14 (depends on 13) The system of claim 13, wherein quantifying a relationship between the most critical delay and the sum of critical delays comprises calculating a p-norm of the sum of delays. ### Claim 15 (depends on 14) The system of claim 14, wherein a solution has a worse relationship between the most critical delay and the sum of critical delays when the solution's p-norm of the sum of delays comprises a higher value than a p-norm of the sum of delays of at least one other solution of the set of solutions. ### Claim 16 (depends on 14) The system of claim 14, wherein the set of solutions is created according to a set of design parameters; and wherein a solution has a worse relationship between the most critical delay and the sum of delays when the solution's relationship is associated with a value which deviates from the design parameters by a greater margin than a value associated with the relationship between the most critical delay and the sum of critical delays of at least one other solution of the set of solutions. ### Claim 17 (depends on 13) The system of claim 13, wherein the method further comprises determining a load cap and a buffer cost for each solution of the set of solutions. ### Claim 18 (depends on 17) The system of claim 17, wherein the method further comprises comparing each solution's load cap and buffer cost with the load cap and buffer cost of each other solution in the set of solutions, wherein each solution has a characterization and the characterization comprises the solution's load cap, buffer cost, and relationship between the most critical delay and the sum of critical delays; and wherein the identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution of the set of solutions to have a worse relationship than the other solutions in the set of solutions further comprises identifying, based on the comparing of each solution's load cap and buffer cost with the load cap and buffer cost of each other solution in the set of solutions, at least one solution of the set of solutions to have a worse characterization than the other solutions in the set of solutions. ### Claim 19 (depends on 18) The system of claim 18, wherein a solution has a worse characterization if the solution's load cap has a lower value and the solution's buffer cost has a higher value than a load cap and a buffer cost of at least one other solution of the set of solutions. ### Claim 20 A computer program product for optimizing timing in a VLSI circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to perform a method comprising: determining a most critical delay and a sum of delays for each solution of a set of buffer solutions for the VLSI circuit; quantifying, for each solution, a relationship between the most critical delay and the sum of delays; comparing each solution's relationship to the relationship of each other solution in the set of solutions; identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution of the set of solutions to have a worse relationship between the most critical delay and the sum of delays than the other solutions in the set of solutions; and pruning the at least one solution from the set of solutions.