# US 10,503,689 B2 · Image processor I/O unit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,689 B2 - Document ID: US10503689B2 - Status: Granted - Kind: B2 - Application number: 15/595,316 - Filed: 2017-05-15 - Published: 2018-11-15 - Granted: 2019-12-10 - Earliest claimed: 2017-05-15 - Assignees: Google Inc. - Applicants: Google LLC - Inventors: Asif Khan; Jason Redgrave; Neeti Desai; David Warren - Web page: https://patentgrep.com/patent/US10503689B2 ## CPC - G06F 15/78: comprising a single central processing unit - G06F 15/7867: {with reconfigurable architecture} - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract An image processor is described. The image processor includes a storage circuit to store segments of input image data received in a raster scan format from a camera. The image processor further includes a reformatting circuit to convert the segments of input image data into a block image format. The image processor further includes a processor comprising a two-dimensional execution lane array and a two-dimensional shift register array. The two-dimensional shift register array is to store the input image data that has been formatted into the block image format. The execution lane array is to execute instructions that operate on the image data from the two-dimensional shift register array. ## Claims ### Claim 1 An image processor, comprising: a storage circuit to store segments of input image data received in a raster scan format; a reformatting circuit to convert the segments of input image data into a block image format, wherein the reformatting circuit comprises register space to keep pointers that point to the segments of the input image data, and wherein the reformatting circuit is configured to recognize when a block of the input image data has been stored in the storage circuit and cause segments within the storage circuit that correspond to the block to be read from the storage circuit by referring to the pointers in the register space; a processor comprising a two-dimensional execution lane array and a two-dimensional shift register array, the two-dimensional shift register array to store the input image data that has been formatted into the block image format, the execution lane array to execute instructions that operate on the image data from the two-dimensional shift register array. ### Claim 2 (depends on 1) The image processor of claim 1 wherein the pointers are organized in the register space to have a first dimension that corresponds to a row width of the raster scan format and to have a second dimension that corresponds to a pixel height of the block format. ### Claim 3 (depends on 1) The image processor of claim 1 wherein the reformatting circuit supports any of the following: configurable segment sizes; configurable raster scan row width sizes; configurable block pixel height sizes. ### Claim 4 (depends on 1) The image processor of claim 1 wherein the reformatting circuit is also to perform output block image to output image raster scan conversion. ### Claim 5 (depends on 1) The image processor of claim 1 wherein the reformatting circuit supports multiple raster scan to block image conversion channels. ### Claim 6 A computing system, comprising: a) one or more general purpose processor cores; b) a system memory c) a memory controller coupled to the system memory; d) an image processor comprising i), ii) and iii) below: i) a storage circuit to store segments of input image data received in a raster scan format; ii) a reformatting circuit to convert the segments of input image data into a block image format, wherein the reformatting circuit comprises register space to keep pointers that point to the segments of the input image data, and wherein the reformatting circuit is configured to recognize when a block of the input image data has been stored in the storage circuit and cause segments within the storage circuit that correspond to the block to be read from the storage circuit by referring to the pointers in the register space; iii) a processor comprising a two-dimensional execution lane array and a two-dimensional shift register array, the two-dimensional shift register array to store the input image data that has been formatted into the block image format, the execution lane array to execute instructions that operate on the image data from the two-dimensional shift register array. ### Claim 7 (depends on 6) The computing system of claim 6 wherein the pointers are organized in the register space to have a first dimension that corresponds to a row width of the raster scan format and to have a second dimension that corresponds to a pixel height of the block format. ### Claim 8 (depends on 6) The computing system of claim 6 wherein the reformatting circuit supports any of the following: configurable segment sizes; configurable raster scan row width sizes; configurable block pixel height sizes. ### Claim 9 (depends on 6) The computing system of claim 6 wherein the reformatting circuit is also to perform output block image to output image raster scan conversion. ### Claim 10 (depends on 6) The computing system of claim 6 wherein the reformatting circuit supports multiple raster scan to block image conversion channels. ### Claim 11 A method, comprising: storing input image data received in a raster scan format as segments within a storage circuit; reformatting the input image data into a block image format by reading certain ones of the segments from the storage circuit, comprising keeping pointers within register space that point to the segments of the input image data, and recognizing when a block of the input image data has been stored in the storage circuit and causing segments within the storage circuit that correspond to the block to be read from the storage circuit by referring to the pointers in the register space; and, processing the block image formatted input image data with a processor comprising a two-dimensional execution lane array and a two-dimensional shift register array. ### Claim 12 (depends on 11) The method of claim 11, wherein the pointers are organized in the register space to have a first dimension that corresponds to a row width of the raster scan format and to have a second dimension that corresponds to a pixel height of the block format. ### Claim 13 (depends on 11) The method of claim 11 further comprising performing any of the following to perform the reformatting: configuring a segment size; configuring a raster scan row width size; configuring a block pixel height size. ### Claim 14 (depends on 11) The method of claim 11 further comprising storing block output image data as output segments into the storage circuit and reading certain ones of the output segments from the storage circuit to form raster scan formatted output image data.