# US 10,503,687 B2 · Multi-host peripheral component interconnect express (PCIe) switching based on interrupt vector from PCIe device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,687 B2 - Document ID: US10503687B2 - Status: Granted - Kind: B2 - Application number: 15/490,490 - Filed: 2017-04-18 - Published: 2018-10-18 - Granted: 2019-12-10 - Earliest claimed: 2017-04-18 - Assignees: Western Digital Technologies, Inc. - Applicants: Western Digital Technologies, Inc. - Inventors: Berck Nash; Michael Walker; Randall Hess - Web page: https://patentgrep.com/patent/US10503687B2 ## CPC - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - G06F 13/24: using interrupt (G06F13/32 takes precedence) - G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)} - G06F 13/404: {with address mapping} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Described herein are enhancements for managing multi-host Peripheral Component Interconnect Express (PCIe) switching. In one implementation, a system includes one or more PCIe devices and a PCIe switch configured to receive a first interrupt corresponding to a first interrupt vector from a PCIe device, wherein the first interrupt vector comprises at least a virtual address and a first data value. The switch is further configured to translate the first interrupt vector into a second interrupt vector, wherein the second interrupt vector comprises a second address and a second data value, and transfer a second interrupt using the second interrupt vector to a host of a plurality of hosts that corresponds to the second interrupt vector. ## Claims ### Claim 1 A computing apparatus comprising: one or more computer readable storage media; a processing system operatively coupled with the one or more computer readable storage media; and program instructions stored on the one or more computer readable storage media to operate a Peripheral Component Interconnect Express (PCIe) switch that, when read and executed by the processing system, direct the processing system to at least: receive a first interrupt corresponding to a first interrupt vector from a PCIe device, wherein the first interrupt vector comprises at least a virtual address and a first data value; translate the first interrupt vector into a second interrupt vector, wherein the second interrupt vector comprises a second address and a second data value; and transfer a second interrupt using the second interrupt vector to a host of a plurality of hosts that corresponds to the second interrupt vector. ### Claim 2 (depends on 1) The computing apparatus of claim 1, wherein the program instructions further direct the processing system to: maintain at least one data structure for the plurality of hosts, wherein the at least one data structure comprises a plurality of interrupt vectors received from the plurality of hosts for one or more PCIe devices coupled to the PCIe switch to provide interrupts to the plurality of hosts. ### Claim 3 (depends on 2) The computing apparatus of claim 2, wherein the program instructions further direct the processing system to: for each interrupt vector in the plurality of interrupt vectors received from the plurality of hosts, provide a virtual interrupt vector to a corresponding PCIe device in the one or more PCIe devices coupled to the PCIe switch, wherein the virtual interrupt vector comprises at least a different address than the interrupt vector. ### Claim 4 (depends on 1) The computing apparatus of claim 1, wherein the PCIe device comprises a data storage device. ### Claim 5 (depends on 1) The computing apparatus of claim 1, wherein the PCIe device comprises a Non-Volatile Memory express (NVMe) device. ### Claim 6 (depends on 1) The computing apparatus of claim 1, wherein the plurality of hosts comprises a plurality of computers. ### Claim 7 (depends on 1) The computing apparatus of claim 1, wherein the program instructions to translate the first interrupt vector into a second interrupt vector direct the processing system to apply an addressing offset to the first interrupt vector to generate the second interrupt vector. ### Claim 8 (depends on 1) The computing apparatus of claim 1, wherein the first data value is equivalent to the second data value. ### Claim 9 (depends on 1) The computing apparatus of claim 1, wherein the first data value is different than the second data value. ### Claim 10 A system comprising: one or more Peripheral Component Interconnect Express (PCIe) devices; and a PCIe switch configured to: receive a first interrupt corresponding to a first interrupt vector from a PCIe device, wherein the first interrupt vector comprises at least a virtual address and a first data value; translate the first interrupt vector into a second interrupt vector, wherein the second interrupt vector comprises a second address and a second data value; and transfer a second interrupt using the second interrupt vector to a host of a plurality of hosts that corresponds to the second interrupt vector. ### Claim 11 (depends on 10) The system of claim 10, wherein the PCIe switch is further configured to maintain at least one data structure for the plurality of hosts, wherein the at least one data structure comprises a plurality of interrupt vectors received from the plurality of hosts for one or more PCIe devices coupled to the PCIe switch to provide interrupts to the plurality of hosts. ### Claim 12 (depends on 11) The system of claim 11, wherein the PCIe switch is further configured to, for each interrupt vector in the plurality of interrupt vectors received from the plurality of hosts, provide a virtual interrupt vector to a corresponding PCIe device in the one or more PCIe devices coupled to the PCIe switch, wherein the virtual interrupt vector comprises at least a different address than the interrupt vector. ### Claim 13 (depends on 10) The system of claim 10, wherein the PCIe device comprises a data storage device. ### Claim 14 (depends on 10) The system of claim 10, wherein the PCIe device comprises a Non-Volatile Memory express (NVMe) device. ### Claim 15 (depends on 10) The system of claim 10, wherein the plurality of hosts comprises a plurality of computers. ### Claim 16 (depends on 10) The system of claim 10, wherein the PCIe switch configured to translate the first interrupt vector into a second interrupt vector is configured to apply an addressing offset to the first interrupt vector to generate the second interrupt vector. ### Claim 17 (depends on 10) The system of claim 10, wherein the first data value is equivalent to the second data value. ### Claim 18 (depends on 10) The system of claim 10, wherein the first data value is different than the second data value. ### Claim 19 An apparatus comprising: means for receiving a first interrupt corresponding to a first interrupt vector from a PCIe device, wherein the first interrupt vector comprises at least a virtual address and a first data value; means for translating the first interrupt vector into a second interrupt vector, wherein the second interrupt vector comprises a second address and a second data value; and means for transferring a second interrupt using the second interrupt vector to a host of a plurality of hosts that corresponds to the second interrupt vector. ### Claim 20 (depends on 19) The apparatus of claim 19, further comprising: means for maintaining at least one data structure for the plurality of hosts, wherein the at least one data structure comprises a plurality of interrupt vectors received from the plurality of hosts for one or more PCIe devices coupled to a PCIe switch to provide interrupts to the plurality of hosts; and means for providing, for each interrupt vector in the plurality of interrupt vectors received from the plurality of hosts, a virtual interrupt vector to a corresponding PCIe device in the one or more PCIe devices coupled to the PCIe switch, wherein the virtual interrupt vector comprises at least a different address than the interrupt vector.