# US 10,503,686 B2 · SPI interface with automatic slave select generation

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,503,686 B2
- Document ID: US10503686B2
- Status: Granted
- Kind: B2
- Application number: 15/373,219
- Filed: 2016-12-08
- Published: 2017-06-15
- Granted: 2019-12-10
- Earliest claimed: 2015-12-09
- Assignees: Microchip Technology Incorporated
- Applicants: Microchip Technology Incorporated
- Inventors: Kevin Kilzer; Shyamsunder Ramanathan; Sai Karthik Rajaraman; Justin Milks
- Web page: https://patentgrep.com/patent/US10503686B2

## CPC

- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- G06F 13/4291: {using a clocked protocol}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A serial peripheral interface (SPI) module, comprising a transceiver, the transceiver including a clock line, a data line and at least one slave select line. The SPI also comprises an interface circuit configured to operate in an automatic slave select mode, wherein the interface circuit is configured to automatically assert the slave select line at least one clock before a first clock edge is generated.

## Claims

### Claim 1

A serial peripheral interface (SPI) module, comprising:
a transceiver comprising a clock line, a data line and at least one slave select line and being configurable to perform data transmission according to the SPI protocol; and
an interface circuit configured to operate in a first operating mode and in a second operating mode, wherein in the first operating mode, the slave select line must be controlled manually and in the second operating mode upon a request to transfer data to a slave device, the interface circuit is configured to automatically assert the slave select line at least one clock before a first clock edge is generated and maintained asserted for a plurality of clock cycles while data is transferred.

### Claim 2 (depends on 1)

The module of claim 1, wherein, in the second operating mode, the interface circuit is further configured to maintain the slave select line as asserted until a transfer count reaches zero.

### Claim 3 (depends on 1)

The module of claim 1, wherein, in the second operating mode, the interface circuit is further configured to de-assert the slave select line a predetermined time after a final clock edge.

### Claim 4 (depends on 1)

The module of claim 1, wherein, in the second operating mode, the interface circuit is further configured to de-assert the slave select line one-half baud clock after a final clock edge.

### Claim 5 (depends on 1)

The module of claim 1, wherein the interface circuit is further configured to operate in a programmable size byte transfer mode and in a programmable packet transfer mode.

### Claim 6 (depends on 1)

The module of claim 1, wherein the interface circuit is further configured to operate in a programmable size byte transfer mode, wherein each byte comprises a programmable number of bits.

### Claim 7 (depends on 1)

The module of claim 1, wherein the interface circuit is further configured to operate in a programmable packet transfer mode, wherein:
a total number of bits to be transferred is programmable;
a first parameter defines the number of 8-bit bytes to be transferred for a packet; and
a second parameter defines the number of bits of a last transfer for the packet.

### Claim 8 (depends on 1)

The module of claim 1, wherein, in the second operating mode, the interface circuit is further configured to assert the slave select line based upon a transfer count including a nonzero value.

### Claim 9 (depends on 1)

The module of claim 1, wherein the interface circuit is further configured to assert the slave select line upon determination of an override of the automatic slave select mode.

### Claim 10 (depends on 1)

The module of claim 1, wherein the interface circuit is further configured to:
assert the slave select line upon determination of an override of the automatic slave select mode; and
after removal of the override of the automatic slave select mode, evaluate a transfer count to determine whether to de-assert the slave select line.

### Claim 11 (depends on 1)

A microcontroller comprising a module according to claim 1.

### Claim 12

A method of serial protocol interface data transfer according to the SPI protocol, comprising:
communicating from a master element to a slave element using a clock line, a data line and at least one slave select line; and
programming the master to operate in an automatic slave select mode;
when operating in the automatic slave select mode, upon a request to transfer data to a slave device including automatically asserting the slave select line at least one clock before a first clock edge is generated and maintained asserted for a plurality of clock cycles while data is transferred.

### Claim 13 (depends on 12)

The method of claim 12, further comprising maintaining the slave select line as asserted until a transfer count reaches zero.

### Claim 14 (depends on 12)

The method of claim 12, further comprising de-asserting the slave select line a predetermined time after a final clock edge.

### Claim 15 (depends on 12)

The method of claim 12, further comprising de-asserting the slave select line one-half baud clock after a final clock edge.

### Claim 16 (depends on 12)

The method of claim 12, further comprising operating in a programmable size byte transfer mode and in a programmable packet transfer mode.

### Claim 17 (depends on 12)

The method of claim 12 further comprising operating in a programmable size byte transfer mode, wherein each byte comprises a programmable number of bits.

### Claim 18 (depends on 12)

The method of claim 12, further comprising operating in a programmable packet transfer mode, wherein:
a total number of bits to be transferred is programmable;
a first parameter defines the number of 8-bit bytes to be transferred for a packet; and
a second parameter defines the number of bits of a last transfer for the packet.

### Claim 19 (depends on 12)

The method of claim 12, further comprising asserting the slave select line based upon a transfer count including a nonzero value.

### Claim 20 (depends on 12)

The method of claim 12, further comprising asserting the slave select line upon determination of an override of the automatic slave select mode.

### Claim 21 (depends on 12)

The method of claim 12, further comprising:
asserting the slave select line upon determination of an override of the automatic slave select mode; and
after removal of the override of the automatic slave select mode, evaluating a transfer count to determine whether to de-assert the slave select line.

### Claim 22

A microcontroller comprising a serial peripheral interface (SPI) module, wherein the SPI module comprises:
a transceiver comprising a clock line, a data line and at least one slave select line and being configurable to perform data transmission according to the SPI protocol; and
an interface circuit configured to operate in in an automatic slave select operating mode, in which upon a request to transfer data to a slave device issued by the microcontroller to the SPI module, the interface circuit is configured to automatically assert the slave select line at least one clock before a first clock edge and associated data is generated without requiring additional software to assert the slave select line and maintained asserted for a plurality of clock cycles while data is transferred.