# US 10,503,685 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,685 B2 - Document ID: US10503685B2 - Status: Granted - Kind: B2 - Application number: 15/252,417 - Filed: 2016-08-31 - Published: 2017-09-07 - Granted: 2019-12-10 - Earliest claimed: 2016-03-04 - Assignees: Toshiba Memory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Masayuki Dohi - Web page: https://patentgrep.com/patent/US10503685B2 ## CPC - G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)} - H05K 5/0278: {of USB type (details relating to connectors H01R27/00)} - H05K 7/2039: {characterised by the heat transfer by conduction from the heat generating element to a dissipating body (arrangements for increasing/decreasing heat-transfer, e.g. fins details, F28F13/00)} - G06F 2213/0042: Universal serial bus [USB] - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ## Abstract According to one embodiment, a semiconductor memory device includes a first tube, a case, a substrate, a memory, a controller, and a first layer. The case is connected to the first tube. The substrate includes a first portion inside the first tube. The first layer covers an inner face of the first tube, is interposed between the first portion and the first tube, and has a thermal conductivity higher than a thermal conductivity of the first tube. ## Claims ### Claim 1 A semiconductor memory device comprising: a first tube which includes an inner face and has a first thermal conductivity; a case connected to the first tube; a substrate which includes a first portion inside the first tube, on which an electrode is mounted, and a second portion inside the case; a memory mounted on the substrate; a controller mounted on the substrate and configured to control the memory; and a first layer which is interposed between the first portion of the substrate and the inner face of the first tube, is in contact or covered with at least a portion of the inner face of the first tube, and has a second thermal conductivity higher than the first thermal conductivity of the first tube. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the case includes an inner surface facing the second portion and an outer face on an opposite side of the inner surface, and the first tube is formed integrally with at least a portion of the outer face of the case. ### Claim 3 (depends on 2) The semiconductor memory device according to claim 2, wherein the first tube is formed integrally with the case. ### Claim 4 (depends on 3) The semiconductor memory device according to claim 3, wherein the first layer includes a second tube covering the inner face of the first tube. ### Claim 5 (depends on 3) The semiconductor memory device according to claim 3, wherein the inner face of the first tube includes a first face, a second face facing the first face, a third face connecting one end of the first face and one end of the second face to each other, and a fourth face connecting the other end of the first face and the other end of the second face to each other, the first layer includes a first covering portion covering the first face, a second covering portion covering the second face, a third covering portion covering the third face, and a fourth covering portion covering the fourth face, and the first covering portion, the second covering portion, the third covering portion, and the fourth covering portion are mutually connected. ### Claim 6 (depends on 5) The semiconductor memory device according to claim 5, wherein a portion of the first layer is in contact with the first portion. ### Claim 7 (depends on 6) The semiconductor memory device according to claim 6, wherein the first portion includes a first surface, a second surface positioned on an opposite side of the first surface, a third surface connecting one end of the first surface and one end of the second surface to each other, and a fourth surface connecting the other end of the first surface and the other end of the second surface to each other, the second surface is opposed to the second face, the electrode mounted on the second surface, and the first layer is in contact with the third surface. ### Claim 8 (depends on 7) The semiconductor memory device according to claim 7, wherein the first layer is made to adhere on the inner face of the first tube. ### Claim 9 (depends on 8) The semiconductor memory device according to claim 8, wherein the first layer is thinner than the first tube. ### Claim 10 (depends on 9) The semiconductor memory device according to claim 9, wherein the first tube includes resin. ### Claim 11 (depends on 10) The semiconductor memory device according to claim 10, wherein the first layer includes metal. ### Claim 12 (depends on 11) The semiconductor memory device according to claim 11, further comprising: a member interposed between the first layer and the first portion; and a second layer covering at least a portion of the member, including a first contact portion which is in contact with the first layer and a second contact portion which is in contact with the first portion and is thermally connected to the first contact portion, and having a third thermal conductivity higher than the first thermal conductivity of the first tube. ### Claim 13 (depends on 12) The semiconductor memory device according to claim 12, wherein the case includes a first cover which is provided with a space in which the second portion is arranged and is connected to the first tube, and a second cover configured to close the space by being attached to the first cover, and the member is connected to the second cover. ### Claim 14 (depends on 13) The semiconductor memory device according to claim 13, further comprising a connector which includes the first tube and the first portion and is configured to be inserted into a female connector conforming to a USB standard. ### Claim 15 (depends on 14) The semiconductor memory device according to claim 14, wherein the first tube includes a first end portion connected to the case and a second end portion which is positioned on an opposite side of the first end portion in a direction from the second portion towards the first portion and is not covered by the first layer. ### Claim 16 A semiconductor memory device being connectable to a host device including a socket which includes a terminal and conforms to a Universal Serial Bus (USB) standard, the semiconductor memory device comprising: a USB connector being insertable into the socket; a substrate including a first portion on which an electrode is mounted and a second portion on which a non-volatile memory and a controller controlling the non-volatile memory are mounted, the electrode being in contact with the terminal when the USB connector is inserted into the socket; and a case accommodating the second portion of the substrate therein, wherein the USB connector includes a tube and a layer, the tube accommodates the first portion of the substrate therein, includes an inner face, has a first thermal conductivity, and is connected to the case, and the layer is interposed between the first portion of the substrate and the inner face of the tube, is in contact or covered with at least a portion of an inner face of the tube, and has a second thermal conductivity higher than the first thermal conductivity of the tube. ### Claim 17 (depends on 16) The semiconductor memory device according to claim 16, wherein the inner face of the tube includes a first face, a second face facing the first face, a third face connecting one end of the first face and one end of the second face to each other, and a fourth face connecting the other end of the first face and the other end of the second face to each other, and the layer includes a first covering portion covering the first face, a second covering portion covering the second face and being opposed to the electrode, a third covering portion covering the third face, and a fourth covering portion covering the fourth face, and the first covering portion, the second covering portion, the third covering portion, and the fourth covering portion are mutually connected. ### Claim 18 (depends on 17) The semiconductor memory device according to claim 17, wherein the layer is thinner than the tube. ### Claim 19 (depends on 18) The semiconductor memory device according to claim 18, wherein the tube is made of resin and the layer is made of metal. ### Claim 20 (depends on 19) The semiconductor memory device according to claim 19, wherein the layer is in contact with the first portion.