# US 10,503,670 B2 · Dynamic per-bank and all-bank refresh > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,670 B2 - Document ID: US10503670B2 - Status: Granted - Kind: B2 - Application number: 15/851,324 - Filed: 2017-12-21 - Published: 2019-06-27 - Granted: 2019-12-10 - Earliest claimed: 2017-12-21 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: Guanhao Shen; Ravindra N. Bhargava; James Raymond Magro; Kedarnath Balakrishnan; Jing Wang - Web page: https://patentgrep.com/patent/US10503670B2 ## CPC - G06F 13/1636: {using refresh} - G06F 13/1642: {with request queuing} - G06F 13/4234: {being a memory bus} - G11C 11/40603: {Arbitration, priority and concurrent access to memory cells for read/write or refresh operations} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Systems, apparatuses, and methods for performing efficient memory accesses in a computing system are disclosed. In various embodiments, a computing system includes computing resources and a memory controller coupled to a memory device. The memory controller determines a memory request targets a given rank of multiple ranks. The memory controller determines a predicted latency for the given rank as an amount of time the pending queue in the memory controller for storing outstanding memory requests does not store any memory requests targeting the given rank. The memory controller determines the total bank latency as an amount of time for refreshing a number of banks which have not yet been refreshed in the given rank with per-bank refresh operations. If there are no pending requests targeting the given rank, each of the predicted latency and the total bank latency is used to select between per-bank and all-bank refresh operations. ## Claims ### Claim 1 A computing system comprising: a communication fabric; one or more computing resources configured to: execute one or more applications; and generate memory access requests; a memory controller coupled to a memory device comprising a plurality of ranks, each rank comprising a plurality of banks; wherein the memory controller is configured to: receive the memory access requests via the communication fabric; receive information identifying the one or more applications; predict a first latency based at least upon the received information, wherein the first latency is an amount of time a pending queue for storing outstanding memory requests does not store any memory requests targeting a given rank of the plurality of ranks; and determine whether to perform an all-bank refresh operation for the given rank or perform a per-bank refresh operation on a given bank of the plurality of banks in the given rank based at least upon comparing the first latency and a second latency of an all-bank refresh operation; in response to receiving an indication to start a refresh interval for the given rank: select one or more refresh operations based upon the first latency; and perform the selected one or more refresh operations on the given rank. ### Claim 2 (depends on 1) The computing system as recited in claim 1, wherein the memory controller is configured to perform a per-bank refresh operation on a given bank of the plurality of banks, in response to determining the first latency is less than the second latency. ### Claim 3 (depends on 1) The computing system as recited in claim 1, wherein the memory controller is configured to determine a third latency as an amount of time for refreshing a number of banks which have not yet been refreshed in the given rank with per-bank refresh operations. ### Claim 4 (depends on 3) The computing system as recited in claim 3, wherein the memory controller is configured to perform the all-bank refresh operation for the given rank, in response to determining: there are no pending memory requests targeting the given rank; the first latency is greater than the second latency; and the third latency is greater than the second latency. ### Claim 5 (depends on 3) The computing system as recited in claim 3, wherein the memory controller is configured to perform a per-bank refresh operation on a given bank of the plurality of banks, in response to determining, there are no pending memory requests targeting the given rank; the first latency is greater than the second latency; and the third latency is less than the second latency. ### Claim 6 (depends on 1) The computing system as recited in claim 1, wherein predicting the first latency comprises identifying which ranks of the plurality of ranks are accessed by the one or more applications. ### Claim 7 (depends on 1) The computing system as recited in claim 1, wherein predicting the first latency comprises identifying power-performance states of the one or more computing resources executing the one or more applications. ### Claim 8 (depends on 1) The computing system as recited in claim 1, wherein predicting the first latency comprises identifying miss rates for a cache memory subsystem for the one or more computing resources. ### Claim 9 A method, comprising: executing, by one or more computing resources, one or more applications; generating, by the one or more computing resources, memory access requests for data stored in a memory device comprising a plurality of ranks, each rank comprising a plurality of banks; receiving, by a memory controller, the memory access requests; receiving, by the memory controller, information identifying the one or more applications; predicting, by the memory controller, a first latency between accesses of a given rank of the plurality of ranks based at least upon the received information; and determining whether to perform an all-bank refresh operation for the given rank or perform a per-bank refresh operation on a given bank of the plurality of banks in the given rank based at least upon comparing the first latency and a second latency of an all-bank refresh operation; in response to receiving an indication to start a refresh interval for the given rank: selecting, by the memory controller, one or more refresh operations based upon the first latency; and performing, by the memory controller, the selected one or more refresh operations on the given rank. ### Claim 10 (depends on 9) The method as recited in claim 9, further comprising performing a per-bank refresh operation on a given bank of the plurality of banks, in response to determining the first latency is less than the second latency. ### Claim 11 (depends on 9) The method as recited in claim 9, further comprising determining a third latency as an amount of time for refreshing a number of banks which have not yet been refreshed in the given rank with per-bank refresh operations. ### Claim 12 (depends on 11) The method as recited in claim 11, further comprising performing the all-bank refresh operation for the given rank, in response to determining: there are no pending memory requests targeting the given rank; the first latency is greater than the second latency; and the third latency is greater than the second latency. ### Claim 13 (depends on 11) The method as recited in claim 11, further comprising performing a per-bank refresh operation on a given bank of the plurality of banks, in response to determining, there are no pending memory requests targeting the given rank; the first latency is greater than the second latency; and the third latency is less than the second latency. ### Claim 14 A memory controller comprising: a first interface for receiving memory access requests generated by one or more computing resources executing one or more applications; a second interface for sending the memory access requests to a memory device comprising a plurality of ranks, each rank comprising a plurality of banks; and control logic, wherein the control logic is configured to: receive information identifying the one or more applications; predict a first latency between accesses of a given rank of the plurality of ranks based at least upon the received information; and determine whether to perform an all-bank refresh operation for the given rank or perform a per-bank refresh operation on a given bank of the plurality of banks in the given rank based at least upon comparing the first latency and a second latency of an all-bank refresh operation; in response to receiving an indication to start a refresh interval for the given rank: select one or more refresh operations based upon the first latency; and perform the selected one or more refresh operations on the given rank. ### Claim 15 (depends on 14) The memory controller as recited in claim 14, wherein the control logic is configured to perform a per-bank refresh operation on a given bank of the plurality of banks, in response to determining the first latency is less than the second latency. ### Claim 16 (depends on 14) The memory controller as recited in claim 14, wherein the control logic is configured to determine a third latency as an amount of time for refreshing a number of banks which have not yet been refreshed in the given rank with per-bank refresh operations. ### Claim 17 (depends on 16) The memory controller as recited in claim 16, wherein the control logic is configured to perform the all-bank refresh operation for the given rank, in response to determining: there are no pending memory requests targeting the given rank; the first latency is greater than the second latency; and the third latency is greater than the second latency.