# US 10,503,662 B2 · Systems, apparatuses, and methods for implementing temporary escalated privilege

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- Number: US 10,503,662 B2
- Document ID: US10503662B2
- Status: Granted
- Kind: B2
- Application number: 13/539,132
- Filed: 2012-06-29
- Published: 2014-01-02
- Granted: 2019-12-10
- Earliest claimed: 2012-06-29
- Assignees: Intel Corporation
- Applicants: Martin G. Dixon; Gilbert Neiger; Robert S. Chappell; Scott D. Rodgers; Barry E. Huntley
- Inventors: Martin G. Dixon; Gilbert Neiger; Robert S. Chappell; Scott D. Rodgers; Barry E. Huntley
- Web page: https://patentgrep.com/patent/US10503662B2

## CPC

- G06F 12/14: Protection against unauthorised use of memory {or access to memory}
- G06F 12/1491: {in a hierarchical protection system, e.g. privilege levels, memory rings}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Embodiments of systems, apparatuses, and methods for temporarily allowing access to a lower privilege level from a higher privilege level.

## Claims

### Claim 1

A processor comprising:
execution circuitry to execute one or more instructions of a program, wherein the program is to operate at different privilege levels including a most privileged level and a lower privilege level;
storage for an indication of, when the program is operating at the most privileged level, whether or not the program is temporarily allowed to access data associated with the lower privilege level without changing privilege levels, wherein the storage for an indication of when the program is operating at the most privileged level whether or not the execution circuitry is allowed to access data associated with the lower privilege level is an EFLAGS register and the indication is bit 18.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the most privileged privilege level is a kernel level and the lower privilege level is a user mode.

### Claim 3 (depends on 2)

The processor of claim 2, wherein the data to be access is in a user mode page.

### Claim 4 (depends on 1)

The processor of claim 1, wherein the indication is to be reset upon an interrupt.

### Claim 5

A method of using temporary privilege while executing a program in a processor comprising:
entering a higher privilege level; and
when in the higher privilege level,
requesting access of data associated with a lower privilege level when in the higher privilege level,
determining if the access request for data associated with a lower privilege level is allowed based upon an indicator set in bit 18 of an EFLAGS register of the processor,
denying the access request when the indicator does not indicate that such a request should be granted, and
allowing the access request when the indicator does indicate that such a request should be granted.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
setting the indicator by pushing the register to a stack, modifying the contents of the register, and popping the register off of the stack in this order.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
setting the indicator by executing a set access flag instruction.

### Claim 8 (depends on 6)

The method of claim 6, further comprising:
upon denying the access request when the indicator does not indicate that such a request should be granted, signaling a page fault.

### Claim 9 (depends on 6)

The method of claim 6, further comprising:
upon denying the access request when the indicator does not indicate that such a request should be granted, signaling a general protection fault.

### Claim 10

A non-transitory tangible machine-readable storage medium including instructions which when executed by a processor cause the processor to perform a method, the method comprising:
entering a higher privileged level; and
when in the higher privilege level,
requesting access of data associated with a lower privilege level when in the higher privilege level,
determining if the access request for data associated with a lower privilege level is allowed based upon an indicator set in bit 18 of an EFLAGS register of the processor,
denying the access request when the indicator does not indicate that such a request should be granted, and
allowing the access request when the indicator does indicate that such a request should be granted.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
setting the indicator by pushing the register to a stack, modifying the contents of the register, and popping the register off of the stack in this order.

### Claim 12 (depends on 10)

The method of claim 10, further comprising:
upon denying the access request when the indicator does not indicate that such a request should be granted, signaling a page fault.