# US 10,503,660 B2 · Technique for determining address translation data to be stored within an address translation cache > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,660 B2 - Document ID: US10503660B2 - Status: Granted - Kind: B2 - Application number: 15/848,397 - Filed: 2017-12-20 - Published: 2019-06-20 - Granted: 2019-12-10 - Earliest claimed: 2017-12-20 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: Abhishek Raja; Michael Filippo - Web page: https://patentgrep.com/patent/US10503660B2 ## CPC - G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] - G06F 12/1036: for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) - G06F 12/0891: using clearing, invalidating or resetting means - G06F 12/1063: {the data cache being concurrently virtually addressed} - G06F 12/109: for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) - G06F 15/7839: {with memory} - G06F 2212/654: Look-ahead translation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus and method are provided for determining address translation data to be stored within an address translation cache. The apparatus comprises an address translation cache having a plurality of entries, where each entry stores address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. Via an interface of the apparatus, access requests are received from a request source, where each access request identifies a virtual address. Prefetch circuitry is responsive to a contiguous access condition being detected from the access requests received by the interface, to retrieve one or more descriptors from a page table, where each descriptor is associated with a virtual page, in order to produce candidate coalesced address translation data relating to multiple contiguous virtual pages. At an appropriate point, the prefetch circuitry triggers the control circuitry to allocate, into a selected entry of the address translation cache, coalesced address translation data that is derived from the candidate coalesced address translation data. Such an approach has been found to provide a particularly efficient mechanism for creating coalesced address translation data for allocating into the address translation cache, without impacting the latency of the servicing of ongoing requests from the request source. ## Claims ### Claim 1 An apparatus comprising: an address translation cache having a plurality of entries, each entry to store address translation data used when converting a virtual address into a corresponding physical address of a memory system; control circuitry to perform an allocation process to determine the address translation data to be stored in each entry; an interface to receive access requests from a request source, each access request identifying a virtual address; and prefetch circuitry, responsive to a contiguous access condition being detected from the access requests received by the interface, to retrieve one or more descriptors from a page table, where each descriptor is associated with a virtual page, in order to produce candidate coalesced address translation data relating to multiple contiguous virtual pages, and to trigger the control circuitry to allocate into a selected entry of the address translation cache coalesced address translation data derived from the candidate coalesced address translation data; wherein: the prefetch circuitry has associated buffer storage in which a buffer entry is allocated to maintain the candidate coalesced address translation data, and the prefetch circuitry is arranged in response to detection of the contiguous access condition: to determine for each retrieved descriptor, with reference to the candidate coalesced address translation data, whether coalescing criteria are met by that retrieved descriptor, and in the presence of said coalescing criteria being met, to use that descriptor to update the candidate coalesced address translation data maintained in the buffer entry; and on a trigger condition, to cause the control circuitry to perform the allocation process to store in the selected entry of the address translation cache the coalesced address translation data derived from the candidate coalesced address translation data maintained in the buffer entry. ### Claim 2 (depends on 1) An apparatus as claimed in claim 1, wherein: the contiguous access condition is detected when a plurality of access requests received at the interface specify virtual addresses within contiguous virtual pages. ### Claim 3 (depends on 2) An apparatus as claimed in claim 2, wherein the prefetch circuitry is arranged to retrieve the one or more descriptors with the aim that the multiple contiguous virtual pages to which the candidate coalesced address translation data relates include one or more additional virtual pages beyond the contiguous virtual pages that resulted in the contiguous access condition being detected. ### Claim 4 (depends on 1) An apparatus as claimed in claim 1, wherein each descriptor is associated with a physical page in the memory system, and the candidate coalesced address translation data relates to multiple contiguous virtual pages that map to multiple physical pages within the memory system that meet specified page alignment criteria. ### Claim 5 (depends on 1) An apparatus as claimed in claim 1, wherein the coalesced address translation data allocated by the control circuitry into the selected entry of the address translation cache is set equal to the candidate coalesced address translation data. ### Claim 6 (depends on 1) An apparatus as claimed in claim 1, wherein: the address translation cache has one or more supported page sizes for coalesced address translation data within the address translation cache; and the control circuitry is responsive to the candidate coalesced address translation data exceeding a supported page size, to perform a fracturing operation in order to derive the coalesced address translation data to be allocated into the address translation cache. ### Claim 7 (depends on 1) An apparatus as claimed in claim 1, wherein the trigger condition comprises at least one of: the candidate coalesced address translation data relating to a determined maximum number of multiple contiguous virtual pages; the candidate coalesced address translation data relating to a maximum supported page size for coalesced address translation data within the address translation cache; the coalescing criteria no longer being met. ### Claim 8 (depends on 1) An apparatus as claimed in claim 1, wherein: each descriptor is associated with a physical page in the memory system; and the prefetch circuitry is arranged to allow the coalescing criteria to be absent for one or more retrieved descriptors whilst continuing to retrieve further descriptors with the aim of updating the candidate coalesced address translation data maintained in the buffer entry prior to the trigger condition occurring; and the candidate coalesced address translation data is arranged to identify any pages for which the candidate coalesced address translation data should not be used. ### Claim 9 (depends on 1) An apparatus as claimed in claim 1, wherein the prefetch circuitry is arranged to determine an initial form of the candidate coalesced address translation data from any address translation data detected to be present in the address translation cache for one or more of the access requests received at the interface that caused the contiguous access condition to be detected. ### Claim 10 (depends on 1) An apparatus as claimed in claim 1, wherein the prefetch circuitry is arranged to perform a series of page table walk operations in order to retrieve the one or more descriptors from the page table, each page table walk operation causing at least one descriptor to be obtained from the page table. ### Claim 11 (depends on 10) An apparatus as claimed in claim 10, wherein for each page table walk operation the prefetch circuitry is arranged: to determine a virtual address to be issued in order to retrieve said at least one descriptor; and to perform a lookup in the address translation cache using the virtual address to determine whether address translation data associated with the virtual address is already present within the address translation cache, and if so to use the address translation data accessed from the address translation cache rather than seeking to retrieve from the page table the descriptor associated with the virtual page identified by the virtual address. ### Claim 12 (depends on 1) An apparatus as claimed in claim 1, wherein: each descriptor is associated with a physical page in the memory system, and the candidate coalesced address translation data relates to multiple contiguous virtual pages that map to multiple physical pages within the memory system that meet specified page alignment criteria; and the prefetch circuitry is arranged to determine whether the coalescing criteria is met by determining whether updating the candidate coalesced address translation data to cover the physical page associated with the descriptor would allow the specified page alignment criteria to continue to be met. ### Claim 13 (depends on 12) An apparatus as claimed in claim 12, wherein said specified page alignment criteria requires the physical pages covered by the candidate coalesced address translation data to be contiguous physical pages. ### Claim 14 (depends on 12) An apparatus as claimed in claim 12, wherein: each descriptor further comprises attribute data identifying a plurality of attributes; and the candidate coalesced address translation data covers physical pages for which attribute match criteria is met; the prefetch circuitry is arranged to determine whether the coalescing criteria is met by further determining whether updating the candidate coalesced address translation data to cover the physical page associated with the descriptor would allow the attribute match criteria to continue to be met. ### Claim 15 (depends on 14) An apparatus as claimed in claim 14, wherein the attribute match criteria allows the plurality of physical pages covered by the candidate coalesced address translation data to have different values for a first subset of the attributes when determining that the attribute match criteria is met. ### Claim 16 (depends on 1) An apparatus as claimed in claim 1, wherein the descriptors used to produce the candidate coalesced address translation data are final level descriptors. ### Claim 17 (depends on 1) An apparatus as claimed in claim 1, wherein when a request is received at the interface from the request source, a lookup operation is performed in both the address translation cache and the buffer storage in order to determine if there is a hit condition. ### Claim 18 An apparatus comprising: an address translation cache having a plurality of entries, each entry to store address translation data used when converting a virtual address into a corresponding physical address of a memory system; control circuitry to perform an allocation process to determine the address translation data to be stored in each entry; an interface to receive access requests from a request source, each access request identifying a virtual address; and prefetch circuitry, responsive to a contiguous access condition being detected from the access requests received by the interface, to retrieve one or more descriptors from a page table, where each descriptor is associated with a virtual page, in order to produce candidate coalesced address translation data relating to multiple contiguous virtual pages, and to trigger the control circuitry to allocate into a selected entry of the address translation cache coalesced address translation data derived from the candidate coalesced address translation data, wherein the apparatus is arranged to continue to process access requests from the request source, in parallel with the operation of the prefetch circuitry in the presence of the contiguous access condition. ### Claim 19 A method of determining address translation data to be stored within an address translation cache having a plurality of entries, each entry for storing address translation data used when converting a virtual address into a corresponding physical address of a memory system, the method comprising: performing an allocation process to determine the address translation data to be stored in each entry; receiving access requests from a request source, each access request identifying a virtual address; responsive to a contiguous access condition being detected from the received access requests, employing prefetch circuitry to retrieve one or more descriptors from a page table, where each descriptor is associated with a virtual page, in order to produce candidate coalesced address translation data relating to multiple contiguous virtual pages; and triggering the allocation process to cause the allocation into a selected entry of the address translation cache of coalesced address translation data derived from the candidate coalesced address translation data; wherein the prefetch circuitry has associated buffer storage in which a buffer entry is allocated to maintain the candidate coalesced address translation data, and in response to detection of the contiguous access condition, the prefetch circuitry: determines for each retrieved descriptor, with reference to the candidate coalesced address translation data, whether coalescing criteria are met by that retrieved descriptor, and in the presence of said coalescing criteria being met, uses that descriptor to update the candidate coalesced address translation data maintained in the buffer entry; and on a trigger condition, causes the allocation process to store in the selected entry of the address translation cache the coalesced address translation data derived from the candidate coalesced address translation data maintained in the buffer entry.