# US 10,503,652 B2 · Sector cache for compression

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- Number: US 10,503,652 B2
- Document ID: US10503652B2
- Status: Granted
- Kind: B2
- Application number: 15/477,058
- Filed: 2017-04-01
- Published: 2018-10-04
- Granted: 2019-12-10
- Earliest claimed: 2017-04-01
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Abhishek R. Appu; Altug Koker; Joydeep Ray; David Puffer; Prasoonkumar Surti; Lakshminarayanan Striramassarma; Vasanth Ranganathan; Kiran C. Veernapu; Balaji Vembu; Pattabhiraman K
- Web page: https://patentgrep.com/patent/US10503652B2

## CPC

- G06F 12/0877: Cache access modes
- G06F 12/0802: Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F 12/0806: Multiuser, multiprocessor or multiprocessing cache systems
- G06F 12/0848: {Partitioned cache, e.g. separate instruction and operand caches}
- G06F 12/0855: Overlapped cache accessing, e.g. pipeline (G06F12/0846 takes precedence)
- G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
- G06F 12/126: with special data handling, e.g. priority of data or instructions, handling errors or pinning
- G06T 1/60: Memory management
- G06F 12/0893: Caches characterised by their organisation or structure
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

## Claims

### Claim 1

A general-purpose graphics processing device comprising:
an instruction cache to receive a stream of instructions;
an instruction unit to execute the stream of instructions;
a general-purpose graphics processing compute block comprising a plurality of execution units;
a shared cache memory communicatively coupled to the plurality of execution units;
a memory interface communicatively coupled to the shared cache memory comprising a processor to:
structure the cache memory is structured into a plurality of sectors, each sector in the plurality of sectors comprising at least a first cache line and a second cache line, wherein the first cache line and the second cache line in each of the plurality of sectors are indicated by a pairing bit field assigned by the processor that associates the first cache line and the second cache line with a sector in the plurality of sectors and which is included with cache access operations and in a cache tag field;
receive a cache access request to the shared cache memory, the cache access request comprising the paring bit field; and
use the pairing bit field to locate the at least a first cache line and a second cache line associated with the cache access request to the shared cache memory; and
a data compression unit communicatively coupled to the cache memory, wherein the data compression unit operates at a sector-level granularity.

### Claim 2 (depends on 1)

The general-purpose graphics processing device of claim 1, wherein the general-purpose graphics processing compute block includes multiple compute clusters, each compute cluster including multiple graphics multiprocessors.

### Claim 3 (depends on 2)

The general-purpose graphics processing device of claim 2, further comprising a processor to match the pairing bit included with a cache access operation to the pairing bit in a cache tag field.

### Claim 4 (depends on 1)

The general-purpose graphics processing device of claim 1, further comprising a processor to implement a victim selection algorithm during a cache eviction.

### Claim 5 (depends on 4)

The general-purpose graphics processing device of claim 4, wherein the victim selection algorithm assigns a high priority to cache sectors which are invalid.

### Claim 6 (depends on 4)

The general-purpose graphics processing device of claim 4, wherein the victim selection algorithm assigns a high priority to cache sectors which are valid and include at least one invalid cacheline.

### Claim 7 (depends on 4)

The general-purpose graphics processing device of claim 4, wherein the victim selection algorithm assigns a low priority to cache sectors which are valid and include at least all invalid cachelines.

### Claim 8 (depends on 1)

The general-purpose graphics processing device of claim 1 wherein the general-purpose graphics processing device is an add-in card connected to the separate general-purpose processor via a system bus.

### Claim 9 (depends on 1)

The general-purpose graphics processing device of claim 1, wherein the plurality of execution units are on a single integrated circuit.

### Claim 10

An electronic device, comprising:
a central processing unit; and
a general-purpose graphics processing device comprising:
an instruction cache to receive a stream of instructions;
an instruction unit to execute the stream of instructions;
a general-purpose graphics processing compute block comprising a plurality of execution units;
a shared cache memory communicatively coupled to the plurality of execution units;
a memory interface communicatively coupled to the shared cache memory comprising a processor to:
structure the cache memory is structured into a plurality of sectors, each sector in the plurality of sectors comprising at least a first cache line and a second cache line, wherein the first cache line and the second cache line in each of the plurality of sectors are indicated by a pairing bit field assigned by the processor that associates the first cache line and the second cache line with a sector in the plurality of sectors and which is included with cache access operations and in a cache tag field;
receive a cache access request to the shared cache memory, the cache access request comprising the paring bit field; and
use the pairing bit field to locate the at least a first cache line and a second cache line associated with the cache access request to the shared cache memory; and
a data compression unit communicatively coupled to the cache memory, wherein the data compression unit operates at a sector-level granularity.

### Claim 11 (depends on 10)

The electronic device of claim 10, wherein the general-purpose graphics processing compute block includes multiple compute clusters, each compute cluster including multiple graphics multiprocessors.

### Claim 12 (depends on 11)

The electronic device of claim 11, further comprising a processor to match the pairing bit included with a cache access operation to the pairing bit in a cache tag field.

### Claim 13 (depends on 10)

The electronic device of claim 10, further comprising a processor to implement a victim selection algorithm during a cache eviction.

### Claim 14 (depends on 13)

The electronic device of claim 13, wherein the victim selection algorithm assigns a high priority to cache sectors which are invalid.

### Claim 15 (depends on 13)

The electronic device of claim 13, wherein the victim selection algorithm assigns a high priority to cache sectors which are valid and include at least one invalid cache line.

### Claim 16 (depends on 13)

The electronic device of claim 13, wherein the victim selection algorithm assigns a low priority to cache sectors which are valid and include at least all invalid cache lines.

### Claim 17 (depends on 10)

The electronic device of claim 10, wherein the general-purpose graphics processing device is an add-in card connected to the separate general-purpose processor via a system bus.

### Claim 18 (depends on 10)

The electronic device of claim 10, wherein the plurality of execution units are on a single integrated circuit.