# US 10,503,647 B2 · Cache allocation based on quality-of-service information

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- Number: US 10,503,647 B2
- Document ID: US10503647B2
- Status: Granted
- Kind: B2
- Application number: 15/882,722
- Filed: 2018-01-29
- Published: 2018-05-31
- Granted: 2019-12-10
- Earliest claimed: 2014-11-28
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Moon Gyung Kim
- Web page: https://patentgrep.com/patent/US10503647B2

## CPC

- G06F 12/084: with a shared cache
- G06F 3/061: {Improving I/O performance}
- G06F 3/0631: {by allocating resources to storage systems}
- G06F 3/0647: {Migration mechanisms}
- G06F 3/0683: {Plurality of storage devices}
- G06F 2212/6042: Allocation of cache space to multiple users or processors
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A cache memory device shared by a plurality of processors includes a cache memory configured to store some of data stored in a main memory and to be accessed by the plurality of processors. A cache controller stores quality-of-service (QoS) information of each of the plurality of processors and differently sets a size of a storage space of the cache memory to be managed by a target processor, based on the QoS information of the target processor.

## Claims

### Claim 1

A system-on-chip comprising:
a first processor;
a second processor;
a cache memory configured to store quality-of-service (QoS) information of each of the first and second processors; and
a cache controller configured to differently set a size of a storage space of the cache memory to be managed by each of the first and second processors, based on the QoS information of each of the first and second processors, wherein:
the cache memory comprises a plurality of entries,
the plurality of entries is divided into two or more entry groups,
the cache controller limits an entry group to be accessed among the two or more entry groups, based on cache size information corresponding to the QoS information, and
when the QoS information of any of the first and second processors is changed, the cache controller sets the size of the storage space of the cache memory based on the changed QoS information.

### Claim 2 (depends on 1)

The system-on-chip of claim 1, wherein the cache controller comprises a size information storage unit configured to store the cache size information.

### Claim 3 (depends on 2)

The system-on-chip of claim 2, wherein the cache controller limits entries to be managed by a target processor among the plurality of entries, based on the cache size information.

### Claim 4 (depends on 2)

The system-on-chip of claim 2, wherein:
the cache memory is an n-way set-associative cache including n ways, wherein n denotes an integer equal to or greater than ‘2’, and
the cache controller limits ways to be managed among the n ways, based on the cache size information.

### Claim 5 (depends on 2)

The system-on-chip of claim 2, wherein, when receiving a transaction from the first processor or the second processor, the cache controller receives a processor identifier, extracts QoS information according to the processor identifier, and extracts cache size information corresponding to the extracted QoS information.

### Claim 6 (depends on 5)

The system-on-chip of claim 5, wherein the cache controller further comprises:
an entry manager configured to provide an available entry list based on the extracted cache size information; and
an entry allocator configured to allocate a new entry or replace an existing entry, among the plurality of entries, with another entry according to the available entry list.

### Claim 7 (depends on 1)

The system-on-chip of claim 1, further comprising a bus via which data and a control signal are exchanged among the first processor, the second processor, the cache memory, and the cache controller.

### Claim 8

A cache memory device shared by a plurality of processors, the cache memory device comprising:
a cache memory configured to store quality-of-service (QoS) information of each of the plurality of processors; and
a cache controller configured to allocate a size of a storage space of the cache memory to be managed by a target processor, based on the QoS information of the target processor, wherein
a number of the plurality of processors is equal to or greater than ‘2’, wherein:
the cache memory comprises a plurality of entries,
the cache controller further comprises:
an entry manager configured to provide an available entry list based on cache size information corresponding to the QoS information, and
an entry allocator configured to allocate a new entry or replace an existing entry, among the plurality of entries, with another entry according to the available entry list, and
when the QoS information of any of the plurality of processors is changed, the cache controller sets the size of the storage space of the cache memory based on the changed QoS information.

### Claim 9 (depends on 8)

The cache memory device of claim 8, wherein the cache controller receives a processor identifier of one of the plurality of processors when a transaction is received from the processor and extracts the QoS information corresponding to the processor identifier.

### Claim 10 (depends on 9)

The cache memory device of claim 9, wherein the cache controller further comprises a size information storage unit configured to store the cache size information.

### Claim 11 (depends on 10)

The cache memory device of claim 10, wherein the cache controller limits entries to be managed among the plurality of entries according to the cache size information.

### Claim 12 (depends on 10)

The cache memory device of claim 10, wherein:
the plurality of entries is divided into two or more entry groups, and
the cache controller limits an entry group to be managed among the two or more entry groups according to the cache size information.

### Claim 13

A method, executed by a cache memory controller, of allocating memory of a cache, shared in common by multiple processors, to each of the processors, the method comprising:
receiving, from each of the processors, an electronic communication comprising an indication of the processor's identification;
identifying, for each processor based upon the indication of the processor's identification, quality-of-service (QoS) information identifying a QoS required by the processor;
allocating memory of the cache to each of the processors in accordance with the identified QoS information for the processor;
determining whether a data request from a first of the processors is stored in the memory allocated to the first processor;
determining whether the memory allocated to the first processor should be expanded;
allocating additional memory to the first processor, upon determining that the memory allocated to the first processor should be expanded; and
when the QoS information is changed, allocating memory of the cache to each of the processors in accordance with the change QoS information for the processor.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
determining whether a data entry stored in the memory of the cache allocated to the first processor should be replaced with the data requested by the first processor, upon determining that the memory allocated to the first processor should not be expanded; and
replacing the data entry with the data requested by the first processor, upon determining that the data entry stored in the memory of the cache allocated to the first processor should be replaced with the data requested by the first processor.

### Claim 15 (depends on 13)

The method of claim 13, wherein allocating the memory of the cache to each of the processors comprises:
identifying cache size information corresponding to the QoS information for the processor, and
allocating the memory of the cache to the processors in accordance with the identified cache size information.