# US 10,503,641 B2 · Cache coherence for processing in memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,641 B2 - Document ID: US10503641B2 - Status: Granted - Kind: B2 - Application number: 15/169,118 - Filed: 2016-05-31 - Published: 2017-11-30 - Granted: 2019-12-10 - Earliest claimed: 2016-05-31 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: Michael W. Boyer; Nuwan Jayasena - Web page: https://patentgrep.com/patent/US10503641B2 ## CPC - G06F 12/0817: using directory methods - G06F 12/0822: {Copy directories (local copy tags for implementing a bus snooping protocol G06F12/0831)} - G06F 2212/1004: Compatibility, e.g. with legacy hardware - G06F 2212/1016: Performance improvement - G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A cache coherence bridge protocol provides an interface between a cache coherence protocol of a host processor and a cache coherence protocol of a processor-in-memory, thereby decoupling coherence mechanisms of the host processor and the processor-in-memory. The cache coherence bridge protocol requires limited change to existing host processor cache coherence protocols. The cache coherence bridge protocol may be used to facilitate interoperability between host processors and processor-in-memory devices designed by different vendors and both the host processors and processor-in-memory devices may implement coherence techniques among computing units within each processor. The cache coherence bridge protocol may support different granularity of cache coherence permissions than those used by cache coherence protocols of a host processor and/or a processor-in-memory. The cache coherence bridge protocol uses a shadow directory that maintains status information indicating an aggregate view of copies of data cached in a system external to a processor-in-memory containing that data. ## Claims ### Claim 1 A system comprising: a processor-in-memory implementing a first cache coherence protocol, the processor-in-memory comprising: a memory die; and a logic integrated circuit die stacked with the memory die, the logic integrated circuit die comprising: at least one cache of a corresponding processor storing a copy of a data block residing in the memory die; a processor-in-memory directory configured to store a processor-in-memory coherence state of the data block, the processor-in-memory coherence state indicating a status of the copy of the data block in the at least one cache; an intra-processor-in-memory coherence controller configured to maintain data coherence of the data block using contents of the processor-in-memory directory; shadow directory storage configured to store a bridge coherence state of the data block, the bridge coherence state being separate and distinct from the processor-in-memory coherence state, representing all components external to the processor-in-memory as a single additional potential sharing device, and indicating a status of any external copies of the data block stored externally to the processor-in-memory; and bridge protocol translation logic configured to receive coherence messages from intra-host coherence control logic of a host processor coupled to the processor-in-memory, translate the coherence messages from a second cache coherence protocol of the host processor to the first cache coherence protocol, and provide translated coherence messages to bridge protocol control logic, the second cache coherence protocol being different from the first cache coherence protocol; and the bridge protocol control logic configured to maintain data coherence of the data block using the translated coherence messages and contents of the shadow directory storage. ### Claim 2 (depends on 1) The system, as recited in claim 1, wherein the second cache coherence protocol uses block sizes different from block sizes of the first cache coherence protocol. ### Claim 3 (depends on 1) The system, as recited in claim 1, wherein the at least one cache is within a coherence domain of the processor-in-memory maintained by the intra-processor-in-memory coherence controller. ### Claim 4 (depends on 1) The system, as recited in claim 1, wherein the at least one cache is a write-through cache and the bridge coherence state of the data block is a no-host-copy state, a host-read state, or a host-written state, and wherein the no-host-copy state indicates that no host processors in a bridge coherence domain have stored any part of the data block in a host cache, the host-read state indicates that at least one host processor in the bridge coherence domain has read a portion of the data block and may have an unmodified copy of the portion in a host cache, and the host-written state indicates that at least one host processor in the bridge coherence domain has exclusive ownership of the data block and may have written the data block in a host cache. ### Claim 5 (depends on 1) The system, as recited in claim 1, wherein the at least one cache is a write-back cache and the bridge coherence state of the data block is a no-host-copy state, a host-read state, a host-written state, or a processor-in-memory-modified state, wherein the no-host-copy state indicates that no host processors in a bridge coherence domain have stored any part of the data block in a host cache, the host-read state indicates that at least one host processor in the bridge coherence domain has read a portion of the data block and may have an unmodified copy of the portion in a host cache, the host-written state indicates that at least one host processor in the bridge coherence domain has exclusive ownership of the data block and may have written the data block in a host cache, and the processor-in-memory-modified state indicates whether any part of the data block has been modified by the processor-in-memory in the at least one cache. ### Claim 6 (depends on 3) The system, as recited in claim 3, wherein the processor-in-memory further comprises: a memory-side cache outside the coherence domain of the processor-in-memory, wherein the bridge protocol control logic is configured to check the status of any copies of the data block stored in the memory-side cache in response to a memory access to the data block. ### Claim 7 (depends on 1) The system, as recited in claim 1, further comprising: the host processor comprising: host bridge translation logic configured to translate coherence messages received from the processor-in-memory from the first cache coherence protocol to the second cache coherence protocol. ### Claim 8 (depends on 7) The system, as recited in claim 7, wherein the host processor further comprises: a memory-side cache outside a coherence domain of the host and outside a coherence domain of the processor-in-memory, wherein the shadow directory storage captures the status of any copies of the data block stored in the memory-side cache. ### Claim 9 (depends on 7) The system, as recited in claim 7, wherein the host processor further comprises: a host directory configured to store a host coherence state of a host copy of the data block, the host copy being stored within the host processor; and the intra-host coherence control logic configured to maintain data coherence of the host copy of the data block with the data block residing in the processor-in-memory using the host directory. ### Claim 10 A method comprising: storing, in a shadow directory, a bridge coherence state of a data block residing in a memory of a processor-in-memory implementing a first cache coherence protocol, the bridge coherence state being separate and distinct from a processor-in-memory coherence state of the data block, representing all components external to the processor-in-memory as a single additional potential sharing device, and indicating a status of any external copies of the data block stored externally to the processor-in-memory; and storing a copy of the data block in at least one cache of a corresponding processor of the processor-in-memory; storing in a processor-in-memory directory, the processor-in-memory coherence state of the data block, the processor-in-memory coherence state indicating a status of the copy of the data block residing in the at least one cache; and maintaining data coherence of the data block residing in the at least one cache using the processor-in-memory directory; translating coherence messages received from intra-host coherence control logic of a host processor coupled to the processor-in-memory from a second cache coherence protocol of the host processor to the first cache coherence protocol, the second cache coherence protocol being different from the first cache coherence protocol; and maintaining data coherence of the data block using the translated coherence messages and contents of the shadow directory. ### Claim 11 (depends on 10) The method, as recited in claim 10, wherein the second cache coherence protocol uses block sizes different from block sizes of the first cache coherence protocol. ### Claim 12 (depends on 10) The method, as recited in claim 10, wherein maintaining data coherence of the memory of the processor-in-memory comprises updating the bridge coherence state of the data block in response to an access to the data block. ### Claim 13 (depends on 10) The method, as recited in claim 10, wherein maintaining data coherence of the memory of the processor-in-memory comprises: maintaining coherence of the at least one cache with the memory of the processor-in-memory, the at least one cache being within a coherence domain of the processor-in-memory. ### Claim 14 (depends on 10) The method, as recited in claim 10, further comprising: checking a memory-side cache of the processor-in-memory in response to an access of the memory of the processor-in-memory; and implementing a write-through cache policy from a cache in a coherence domain of the processor-in-memory to the memory-side cache of the processor-in-memory, wherein the bridge coherence state of the data block in the shadow directory is a no-host-copy state, a host-read state, or a host-written state, wherein the no-host-copy state indicates that no host processors in a bridge coherence domain have stored any part of the data block in a host cache, the host-read state indicates that at least one host processor in the bridge coherence domain has read a portion of the data block and may have an unmodified copy of the portion in a host cache, and the host-written state indicates that at least one host processor in the bridge coherence domain has exclusive ownership of the data block and may have written the data block in a host cache. ### Claim 15 (depends on 10) The method, as recited in claim 10, further comprising: implementing a write-back cache policy from a cache in a coherence domain of the processor-in-memory to a memory-side cache of the processor-in-memory, wherein the bridge coherence state of the data block in the shadow directory is a no-host-copy state, a host-read state, a host-written state, or a processor-in-memory-modified state, and wherein the no-host-copy state indicates that no host processors in a bridge coherence domain have stored any part of the data block in a host cache, the host-read state indicates that at least one host processor in the bridge coherence domain has read a portion of the data block and may have an unmodified copy of the portion in a host cache, the host-written state indicates that at least one host processor in the bridge coherence domain has exclusive ownership of the data block and may have written the data block in a host cache, and the processor-in-memory-modified state indicates whether any part of the data block has been modified by the processor-in-memory in the at least one cache. ### Claim 16 (depends on 10) The method, as recited in claim 10, wherein maintaining data coherence of the data block comprises generating coherence messages in response to a memory access to the data block. ### Claim 17 (depends on 10) The method, as recited in claim 10, further comprising: storing a host coherence state of a host copy of the data block within a host directory of the host processor; and maintaining data coherence of the host copy of the data block residing in the host processor with the data block residing in the processor-in-memory using the host coherence state. ### Claim 18 An apparatus comprising: a host processor comprising: intra-host coherence control logic configured to maintain data coherence of data blocks residing in a processor-in-memory using a host directory; and host bridge translation logic configured to receive coherence messages from the processor-in-memory, translate the coherence messages from a first cache coherence protocol of the processor-in-memory using a shadow directory of the processor-in-memory to a second cache coherence protocol using the host directory of the host processor, and provide translated coherence messages to the intra-host coherence control logic, the second cache coherence protocol being different from the first cache coherence protocol, wherein the processor-in-memory includes a processor-in-memory directory that stores a processor-in-memory coherence state of any copies of the data blocks stored within at least one cache of a corresponding processor of the processor-in-memory, and wherein the shadow directory stores a bridge coherence state of the data block separate and distinct from the processor-in-memory coherence state, representing all components external to the processor-in-memory as a single additional potential sharing device, and indicating status information for the copies of the data blocks stored in a cache memory of the host processor. ### Claim 19 (depends on 18) The apparatus, as recited in claim 18, wherein the host processor further comprises: the host directory configured to store host coherence state information corresponding to the copies of the data blocks. ### Claim 20 (depends on 18) The apparatus, as recited in claim 18, wherein the second cache coherence protocol uses block sizes different from block sizes of the first cache coherence protocol.