# US 10,503,635 B2 · System and method for adaptive optimization for performance in solid state drives based on segment access frequency

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- Number: US 10,503,635 B2
- Document ID: US10503635B2
- Status: Granted
- Kind: B2
- Application number: 15/273,573
- Filed: 2016-09-22
- Published: 2018-03-22
- Granted: 2019-12-10
- Earliest claimed: 2016-09-22
- Assignees: Dell Products L.P.
- Applicants: Dell Products, LP
- Inventors: Lip Vui Kan; Young Hwan Jang
- Web page: https://patentgrep.com/patent/US10503635B2

## CPC

- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 11/34: Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation {; Recording or statistical evaluation of user activity, e.g. usability assessment}
- G06F 11/3471: {Address tracing}
- G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
- G06F 12/121: using replacement algorithms
- G06F 11/3037: {where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00)}
- G06F 12/0862: with prefetch
- G06F 12/12: Replacement control
- G06F 2201/81: Threshold
- G06F 2201/88: Monitoring involving counting
- G06F 2201/885: Monitoring specific for caches
- G06F 2212/1021: Hit rate improvement
- G06F 2212/1044: Space efficiency improvement
- G06F 2212/2022: Flash memory
- G06F 2212/466: Metadata, control data
- G06F 2212/502: using adaptive policy
- G06F 2212/6028: Prefetching based on hints or prefetch instructions
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7211: Wear leveling
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method and information handling system, including a solid state drive (SSD) memory device having NAND flash memory and an SSD controller to execute instructions of an SSD adaptive profiling engine for random access memory (RAM) cache optimization, are disclosed. The SSD controller is configured to cache a partial flash translation layer (FTL) table in RAM including look-up addresses corresponding to LBA segments in the NAND flash memory having access counts reflecting SSD I/O operations. The SSD controller is further configured to detect an outlier LBA segment having look-up addresses in the cached, partial FTL table, wherein the outlier LBA segment has an I/O access counts at a threshold level below the mean of access counts of other LBA segments represented in the partial FTL table, and to evict the LBA segment look-up address of the outlier LBA segment from the cached portion of the FTL table. The partial FTL table may expanded to accommodate additional look-up addresses when no outlier LBA segments exist. A portion of the RAM not used for caching the partial FTL table may be used as a prefetch cache for I/O access operations.

## Claims

### Claim 1

An information handling system comprising:
a solid state drive (SSD) controller and memory device including NAND flash memory;
the SSD controller executing instructions of an SSD adaptive profiling engine for random access memory (RAM) cache optimization, wherein the SSD controller is configured to:
cache a partial flash translation layer (FTL) table in RAM including look-up addresses corresponding to logical block address (LBA) segments in the NAND flash memory having access counts reflecting SSD input/output (I/O) operations;
detect an outlier LBA segment having a look-up address in the cached, partial FTL table, wherein the outlier LBA segment has an I/O access count at a threshold level below a mean of access counts of other LBA segments represented in the partial FTL table;
evict an LBA segment look-up address associated with the outlier LBA segment from the cached, partial FTL table if an outlier LBA segment is detected; and
expand the partial FTL table cached in the RAM to load a new LBA segment look-up address in the cached, partial FTL table for an LBA segment having an access count within the threshold level of the mean of access counts of the other LBA segments represented in the partial FTL table if no outlier LBA segment is detected.

### Claim 2 (depends on 1)

The information handling system of claim 1 wherein the SSD controller is further configured to replace the evicted LBA segment look-up address associated with the outlier LBA segment with another LBA segment having an access count above a threshold level from the mean of access counts of other LBA segments represented in the partial FTL table.

### Claim 3 (depends on 1)

The information handling system of claim 1 wherein the threshold level for an outlier LBA segment is a standard deviation below the mean of access counts of other LBA segments represented in the partial FTL table.

### Claim 4 (depends on 1)

The information handling system of claim 1 wherein the SSD controller is further configured to designate a remaining portion of the RAM not used for caching the partial FTL table as a pre-fetch data cache for I/O access operations.

### Claim 5 (depends on 1)

The information handling system of claim 1 wherein the SSD controller is further configured to commence the adaptive profiling engine to determine outlier LBA segments upon determining a cache miss in the cached, partial FTL table.

### Claim 6 (depends on 1)

The information handling system of claim 1 wherein the SSD controller is further configured to determine a cache hit for the partial FTL table and increment a segment count for the LBA segment access count corresponding to the hit LBA segment look-up address, and update a database of loaded LBA segment addresses in the cached, partial FTL table with access count metadata.

### Claim 7 (depends on 1)

The information handling system of claim 1 wherein the SSD controller is further configured to update a database of LBA segment usage history in the NAND flash memory with access count data.

### Claim 8 (depends on 7)

The information handling system of claim 7 wherein the SSD controller is further configured to commence the adaptive profiling engine to determine outlier LBA segments upon detecting shutdown of the SSD memory device.

### Claim 9

A computerized method of random access memory (RAM) cache optimization for a solid state drive (SSD) including NAND memory comprising:
executing instructions, via an SSD controller, of an SSD adaptive profiling engine for RAM cache optimization;
caching, in a portion of RAM, a partial flash translation layer (FTL) table including look-up addresses corresponding to logical block address (LBA) segments in the NAND memory having a threshold level of SSD input/output (I/O) accesses;
receiving, at the SSD controller, an SSD I/O access and detecting an FTL table cache miss;
in response to the SSD I/O access FTL table cache miss, executing the adaptive profiling engine to detect whether any outlier LBA segments with cached FTL table look-up addresses have SSD I/O access counts that are below a threshold level relative to a mean of LBA segment access counts for cached LBA segment addresses in the partial FTL table; and
expanding the portion of RAM allocated for the partial FTL table cached therein to accommodate additional look-up addresses when no outlier LBA segments are detected among the cached FTL table look-up addresses.

### Claim 10 (depends on 9)

The computerized method of claim 9 further comprising:
upon determining an outlier LBA segment, evicting the corresponding LBA segment address from the cached, partial FTL table; and
replacing the evicted LBA segment address with a look-up address of an LBA segment having higher SSD I/O access counts.

### Claim 11 (depends on 9)

The computerized method of claim 9 further comprising:
updating a database of LBA segment usage history with an incremented access count reflecting the received SSD I/O access.

### Claim 12 (depends on 9)

The computerized method of claim 9 further comprising:
in response to the SSD controller detecting an FTL table cache hit, incrementing a segment count for the LBA segment access count corresponding to the hit LBA segment look-up address; and
updating a database of loaded LBA segment addresses in the cached, partial FTL table with access count data.

### Claim 13 (depends on 9)

The computerized method of claim 9 wherein the threshold level relative to the mean of LBA segment access counts is an LBA segment access count at a standard deviation threshold level of 2σ below the mean of LBA segment access counts for LBA segments corresponding to cached LBA segment look-up addresses.

### Claim 14 (depends on 12)

The computerized method of claim 12 further comprising:
designating, via the SSD controller, a remaining portion of the RAM not used for caching the partial FTL table as a pre-fetch data cache for I/O access operations.

### Claim 15 (depends on 9)

The computerized method of claim 9 further comprising:
receiving data look-ahead hints from a process optimization software running on an information handling system operating system indicating I/O access operations that are related to the received SSD I/O access; and
pre-fetching data from LBA segments into a pre-fetch cache corresponding to the I/O access operations indicated.

### Claim 16

An information handling system comprising:
a solid state drive (SSD) controller and memory device including NAND flash memory, the SSD controller executing instructions of an SSD adaptive profiling engine for RAM cache optimization, wherein the SSD controller is configured to:
access a database of logical block address (LBA) segment usage history and load a partial flash translation layer (FTL) table into random access memory (RAM) cache if a span of LBA segments with sufficient access counts is below a threshold level percentage of total LBA segments in the NAND flash memory;
detect an outlier LBA segment having a look-up address in the cached, partial FTL table, wherein the outlier LBA segment has an input/output (I/O) access count below a statistical mean of access counts of other LBA segments represented in the partial FTL table; and
evict an LBA segment look-up address corresponding to the outlier LBA segment from the cached, partial FTL table.

### Claim 17 (depends on 16)

The information handling system of claim 16 wherein the SSD controller is further configured to load a full FTL table into the RAM cache if the span of LBA segments with sufficient access counts is above a threshold level percentage of total LBA segments in the NAND flash memory.

### Claim 18 (depends on 16)

The information handling system of claim 16 wherein the SSD controller is further configured to replace the evicted LBA segment look-up address corresponding to the outlier LBA segment with another look-up address of an LBA segment having an access count within a statistical deviation of the mean of access counts of other LBA segments represented in the partial FTL table.

### Claim 19 (depends on 16)

The information handling system of claim 16 wherein the SSD controller is further configured to determine that no outlier LBA segments exist, and to expand the partial FTL table in the RAM cache to load a new LBA segment look-up address in the expanded partial FTL table in the RAM cache upon detecting a cache miss for an I/O access to an LBA segment.

### Claim 20 (depends on 16)

The information handling system of claim 16 wherein the SSD controller is further configured to designate a remaining portion of the RAM cache that is not used for caching the partial FTL table as a pre-fetch data cache for I/O access operations.