# US 10,503,600 B2 · Flash memory devices and error-handling methods thereof

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- Number: US 10,503,600 B2
- Document ID: US10503600B2
- Status: Granted
- Kind: B2
- Application number: 15/922,668
- Filed: 2018-03-15
- Published: 2019-02-07
- Granted: 2019-12-10
- Earliest claimed: 2017-08-07
- Assignees: Silicon Motion, Inc.
- Applicants: Silicon Motion, Inc.
- Inventors: Che-Wei Hsu; Ming-Chang Hsieh
- Web page: https://patentgrep.com/patent/US10503600B2

## CPC

- G06F 11/1402: {Saving, restoring, recovering or retrying}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 11/141: {for bus or memory accesses}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A memory device receiving a host instruction generated by a host includes a flash memory array and a controller. The controller translates the host instruction into operation instructions, queues the operation instructions in a major command queue, and performs an operation on the flash memory array according to the operation instructions. When an error occurs during execution of the operation commands, the controller performs an error-handling process, queues operation commands related to the error-handling process in an auxiliary command queue, sequentially executes the operation commands in the auxiliary command queue, and stops executing the major command queue.

## Claims

### Claim 1

A memory device receiving a host instruction generated by a host, comprising:
a flash memory array; and
a controller, translating the host instruction into a plurality of operation commands, queuing the operation commands in a major command queue, and performing an operation on the flash memory array according to the operation commands, wherein when an error occurs during execution of the operation commands, the controller performs an error-handling process, wherein the controller queues a plurality of operation commands related to the error-handling process in an auxiliary command queue, sequentially executes the operation commands in the auxiliary command queue, and stops executing the major command queue.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein when the operation is a write operation, the error is a write fail, and when the write fail occurs during the write operation, the controller performs the write operation again according to the operation commands in the auxiliary command queue.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein when the operation is an erase operation, the error is an erase fail, and when the erase fail occurs during the erase operation, the controller performs the erase operation again according to the operation command in the auxiliary command queue.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein when the operation is a read operation, the error is an error correction code (ECC) fail, and when an ECC fail occurs during the read operation, the controller performs the read operation again according to the operation commands in the auxiliary command queue.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein when the controller finishes the operation commands in the auxiliary command queue, the controller continues to execute the operation commands in the major command queue.

### Claim 6

An error-handling method adopted in a flash memory array, comprising:
receiving a host instruction generated by a host;
translating the host instruction into a plurality of operation instructions;
queuing the operation commands in a major command queue;
performing an operation on the flash memory array according to the operation commands;
determining whether an error occurs;
when the error occurs, performing an error-handling process and queuing a plurality of operation commands related to the error-handling process in an auxiliary command queue; and
sequentially executing the operation commands in the auxiliary command queue and stopping the execution of the major command queue.

### Claim 7 (depends on 6)

The error-handling method of claim 6, wherein when the operation is a write operation, the error is a write fail, and when the write fail occurs during the write operation, the write operation is performed again according to the operation commands in the auxiliary command queue.

### Claim 8 (depends on 6)

The error-handling method of claim 6, wherein when the operation is an erase operation, the error is an erase fail, and when the erase fail occurs during the erase operation, the erase operation is performed again according to the operation command in the auxiliary command queue.

### Claim 9 (depends on 6)

The error-handling method of claim 6, wherein when the operation is a read operation, the error is an error correction code (ECC) fail, and when the ECC fail occurs during the read operation, the read operation is performed again according to the operation commands in the auxiliary command queue.

### Claim 10 (depends on 6)

The error-handling method of claim 6, further comprising:
when the operation commands in the auxiliary command queue are finished, continuing to execute the operation commands in the major queue.