# US 10,503,584 B1 · Low cost, hardened single board computer for command and data handling > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,584 B1 - Document ID: US10503584B1 - Status: Granted - Kind: B1 - Application number: 15/630,619 - Filed: 2017-06-22 - Granted: 2019-12-10 - Earliest claimed: 2016-06-23 - Assignees: Triad National Security, LLC - Applicants: Los Alamos National Security, LLC - Inventors: Robert Bernard Merl; Paul Stanley Graham - Web page: https://patentgrep.com/patent/US10503584B1 ## CPC - G06F 11/1008: {in individual solid state devices (G06F11/1004 takes precedence)} - G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A radiation hardened single board computer (SBC) includes a processor; static random-access memory (SRAM); non-volatile memory; a field programmable gate array (FPGA); and board-level physical layer interfaces. ## Claims ### Claim 1 A radiation hardened single board computer (SBC) comprising: a processor; static random-access memory (SRAM); non-volatile memory; a field programmable gate array (FPGA); and board-level physical layer interfaces, wherein the SBC is configured to interface with one or more sensor boards not located within the SBC via the board-level physical layer interfaces, wherein each of the sensor boards comprises an FPGA comprising SRAM programming memory, and wherein the FPGA of the SBC is configured to perform automated error detection and correction for errors found in the SRAM programming memory of each of the FPGAs of the one or more sensor boards. ### Claim 2 (depends on 1) The SBC of claim 1, wherein the processor is an application specific integrated circuit. ### Claim 3 (depends on 1) The SBC of claim 1, wherein the FPGA comprises physical layer support for: high-speed serial interfaces; Low-Voltage Differential Signaling (LVDS) interfaces; an Inter-IC (I2C) interface; SpaceWire; and Joint Test Action Group (JTAG) interfaces. ### Claim 4 (depends on 1) The SBC of claim 1, wherein the FPGA comprises a platform for custom hardware co-processing functions to reduce a load on a processor application-specific integrated circuit (ASIC). ### Claim 5 (depends on 1) The SBC of claim 1, wherein the FPGA is configured to manage entire block reads and writes for flash memory. ### Claim 6 (depends on 1) The SBC of claim 1, wherein the SBC is a payload processor for a set of instruments in Earth orbit applications. ### Claim 7 (depends on 1) The SBC of claim 1, wherein the SBC consumes 6.6 W or less. ### Claim 8 (depends on 1) The SBC of claim 1, wherein the SBC is configured to meet MicroTCA standards. ### Claim 9 A field programmable gate array (FPGA) of a radiation hardened single board computer (SBC) configured to provide a platform for custom hardware co-processing functions to reduce a load on a processor application-specific integrated circuit (ASIC) of the SBC, the FPGA comprising: physical layer support for interfaces, wherein the SBC is configured to interface with a sensor board not located within the SBC, and wherein the FPGA of the radiation hardened SBC is configured to perform automated error detection and correction for errors found in static random access memory (SRAM) configuration memory of an FPGA of the sensor board. ### Claim 10 (depends on 9) The FPGA of claim 9, wherein the physical layer support comprises support for: high-speed serial interfaces; Low-Voltage Differential Signaling (LVDS) interfaces; an Inter-IC (I2C) interface; SpaceWire; and Joint Test Action Group (JTAG) interfaces. ### Claim 11 (depends on 9) The FPGA of claim 9, wherein the FPGA is configured to manage entire block reads and writes for flash memory. ### Claim 12 (depends on 9) The FPGA of claim 9, wherein automated error detection and correction comprises: detecting, at the FPGA, an error in the programming memory of the SRAM of the FPGA of the sensor board; interrupting a processor of the sensor board; and fixing, by the processor, the error in the programming memory of the SRAM of the FPGA of the sensor board. ### Claim 13 (depends on 12) The FPGA of claim 12, wherein automated error detection and correction further comprises scrubbing, by the FPGA, the SRAM based FPGA of the sensor board by scanning the programming memory of the SRAM of the FPGA of the sensor board and comparing results of the scan with a set of local checksums. ### Claim 14 (depends on 13) The FPGA of claim 13, wherein the FPGA is configured to perform the scrubbing autonomously without disturbing the processor. ### Claim 15 (depends on 12) The FPGA of claim 12, wherein fixing the error comprises using a known good copy of the programming memory from a deep radiation hardened memory on the SBC. ### Claim 16 A method of providing error detection and correction by a field programmable gate array (FPGA) and processor of a radiation hardened single board computer (SBC), the error detection and correction being for an instrument board not located within the SBC, the method comprising: detecting, at the FPGA, an error in a configuration memory of the instrument board; interrupting a processor of the instrument board, by the FPGA, when the error is detected; and fixing, by the processor, the error in the configuration memory of the instrument board. ### Claim 17 (depends on 16) The method of claim 16, further comprising scrubbing, by the FPGA, a SRAM based FPGA on the instrument board by scanning the configuration memory of the instrument board and comparing results of the scan with a set of local checksums. ### Claim 18 (depends on 17) The method of claim 17, wherein the FPGA performs the scrubbing autonomously without disturbing the processor of the instrument board. ### Claim 19 (depends on 16) The method of claim 16, wherein fixing the error comprises using a known good copy of the configuration memory from a deep radiation hardened memory on the SBC. ### Claim 20 A radiation hardened single board computer (SBC) comprising: a processor; static random-access memory (SRAM); non-volatile memory; a field programmable gate array (FPGA); and board-level physical layer interfaces, wherein the SBC is configured to interface with one or more sensor boards via the board-level physical layer interfaces, wherein the FPGA is configured to perform automated error detection and correction for errors found in a plurality of SRAM programming memory of FPGAs of the sensor boards, and wherein the SBC consumes 6.6 W or less.