# US 10,503,559 B2 · Task mapping method of network-on-chip semiconductor device

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- Number: US 10,503,559 B2
- Document ID: US10503559B2
- Status: Granted
- Kind: B2
- Application number: 14/831,382
- Filed: 2015-08-20
- Published: 2016-10-13
- Granted: 2019-12-10
- Earliest claimed: 2015-04-09
- Assignees: SK hynix Inc.; Research & Business Foundation Sungkyunkwan University
- Applicants: SK hynix Inc.; Research & Business Foundation Sungkyunkwan University
- Inventors: Tae Hee Han; Hyun Joong Kim
- Web page: https://patentgrep.com/patent/US10503559B2

## CPC

- G06F 9/5066: {Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs (mappping at compile time, see G06F8/451)}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A task mapping method of a NoC semiconductor device includes assigning a first task of a plurality of tasks for node control of the NoC semiconductor device to a first node of a first chip; computing tag values of second tasks of the plurality of tasks which are not assigned to the first node; and assigning the second tasks to a second node according to the tag values.

## Claims

### Claim 1

A task mapping method of a network-on-chip (NoC) semiconductor device, the method comprising:
assigning a first task of a plurality of tasks for node control of the NoC semiconductor device to a first node of a first chip, wherein the NoC semiconductor device comprises a plurality of stacked chips including the first chip;
computing tag values of a second tasks of a plurality of tasks that are not assigned to the first node; and
assigning the second tasks to a second node according to the tag values,
wherein the assigning of the second tasks comprises:
comparing the tag values of the second tasks to ‘1’; and
assigning the second tasks to the second node of the first chip when the tag value of the second tasks is larger than ‘1’, and assigning the second tasks to the second node of a second chip when the tag values are equal to or less than ‘1’.

### Claim 2 (depends on 1)

The task mapping method of claim 1, wherein the assigning of the first task comprises:
arranging the tasks in a line; and
selecting the first task among the arranged tasks, and assigning the first task to the first node.

### Claim 3 (depends on 1)

The task mapping method of claim 1, wherein nodes formed in the plurality of chips perform data communication by using through-silicon-vias (TSVs).

### Claim 4 (depends on 1)

The task mapping method of claim 1, wherein the tag value is computed through the following equation:
Tag
i
=
α
×
e
i
⁢
∑
∀
task
⁢
⁢
e
i
(
1
-
α
)
×
∑
∀
r
i
⁢
⁢
w
i
,
j
/
∑
∀
task
⁢
w
i
,
j
⁢
(
0
<
α
<
1
)
,
where α represents a reference value, ei represents a task execution time or computation requirement, ri represents a sub task list related to a task characteristic, and wij represents an average of communications through which data is transmitted from an i-th task to a j-th task.

### Claim 5 (depends on 1)

The task mapping method of claim 1, wherein a node control device for sensing and controlling heat of the node is arranged in the node.