# US 10,503,549 B2 · Time critical tasks scheduling > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,549 B2 - Document ID: US10503549B2 - Status: Granted - Kind: B2 - Application number: 16/027,773 - Filed: 2018-07-05 - Published: 2018-11-01 - Granted: 2019-12-10 - Earliest claimed: 2013-04-09 - Assignees: National Instruments Corporation - Applicants: National Instruments Corporation - Inventors: Sundeep Chandhoke; Herbert K. Salmon, IV - Web page: https://patentgrep.com/patent/US10503549B2 ## CPC - G06F 9/4887: {involving deadlines, e.g. rate based, periodic} - G06F 9/4825: {Interrupt from clock, e.g. time of day} - G06F 2209/486: Scheduler internals - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method and system for scheduling a time critical task. The system may include a processing unit, a hardware assist scheduler, and a memory coupled to both the processing unit and the hardware assist scheduler. The method may include receiving timing information for executing the time critical task, the time critical task executing program instructions via a thread on a core of a processing unit and scheduling the time critical task based on the received timing information. The method may further include programming a lateness timer, waiting for a wakeup time to obtain and notifying the processing unit of the scheduling. Additionally, the method may include executing, on the core of the processing unit, the time critical task in accordance with the scheduling, monitoring the lateness timer, and asserting a thread execution interrupt in response to the lateness timer expiring, thereby suspending execution of the time critical task. ## Claims ### Claim 1 An apparatus for scheduling tasks, the apparatus comprising: a hardware assist scheduler associated with physical hardware, wherein the hardware assist scheduler is configured to: receive timing information for executing a time critical task, wherein the time critical task is associated with a process of the physical hardware and wherein the time critical task executes program instructions via a thread on a core of a processing unit, wherein the processing unit is configured to communicate with the hardware assist scheduler; determine a schedule for the time critical task based on received timing information, wherein the schedule comprises a wakeup time, a specified thread bandwidth, and an overall thread deadline, wherein the overall thread deadline is based on a cycle time and suspend latency of the thread; and cause the core of the processing unit to execute the time critical task according to the schedule. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the hardware assist scheduler is further configured to: suspend execution of the time critical task. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein said suspending execution of the time critical task is in response to expiration of a lateness timer. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the lateness timer is based on the wakeup time. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the hardware assist scheduler is further configured to: notify the processing unit that the thread is in an idle state, wherein the idle state indicates that the thread is awake and ready to resume execution and execute the time critical task in accordance with the schedule. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein to notify the processing unit, the hardware assist scheduler is further configured to: perform a memory write to a memory monitored by the processing unit. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the overall thread deadline is based on the difference between the cycle time and the suspend latency. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the schedule further comprises a time critical task deadline. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the thread comprises a multiplexed thread, wherein the multiplexed thread is executed on the core of the processing unit, and wherein the multiplexed thread comprises: one or more time critical tasks; and a best effort task. ### Claim 10 A non-transitory computer readable memory medium storing program instructions executable by at least one processor to: determine a schedule for a time critical task based on received timing information, wherein the schedule comprises a wakeup time, a specified thread bandwidth, and an overall thread deadline, wherein the overall thread deadline is based on a cycle time and suspend latency of the thread; and execute the time critical task according to the schedule, wherein the time critical task executes program instructions via a thread on a core of a processing unit in accordance with the schedule. ### Claim 11 (depends on 10) The non-transitory computer readable memory medium of claim 10, wherein the program instructions are further executable to: suspend execution of the time critical task. ### Claim 12 (depends on 11) The non-transitory computer readable memory medium of claim 11, wherein to suspend execution of the time critical task, the program instructions are further executable to: perform a memory write to a memory monitored by the processing unit. ### Claim 13 (depends on 10) The non-transitory computer readable memory medium of claim 10, wherein the overall thread deadline is based on the difference between the cycle time and the suspend latency. ### Claim 14 (depends on 10) The non-transitory computer readable memory medium of claim 10, wherein to determine the schedule, the program instructions are further executable to: determine a thread cycle time. ### Claim 15 (depends on 10) The non-transitory computer readable memory medium of claim 10, wherein the thread comprises a multiplexed thread, wherein the multiplexed thread is executed on the core of the processing unit, and wherein the multiplexed thread comprises: one or more time critical tasks; and a best effort task. ### Claim 16 A method for monitoring a time critical task, the method comprising: determining a schedule for the time critical task based on received timing information, wherein the schedule comprises a wakeup time, a specified thread bandwidth, and an overall thread deadline, wherein the overall thread deadline is based on a cycle time and suspend latency of the thread; and executing the time critical task according to the schedule, wherein the time critical task executes program instructions via a thread on a core of a processing unit in accordance with the schedule. ### Claim 17 (depends on 16) The method of claim 16, wherein the time critical task is a function of the overall thread deadline and the specified thread bandwidth. ### Claim 18 (depends on 16) The method of claim 16, further comprising: notifying the processing unit that the thread is in an idle state, wherein the idle state indicates that the thread is awake and ready to resume execution and execute the time critical task in accordance with the schedule. ### Claim 19 (depends on 15) The method of claim 15, wherein the overall thread deadline is based on the difference between the cycle time and the suspend latency. ### Claim 20 (depends on 15) The method of claim 15, wherein the thread comprises a multiplexed thread, wherein the multiplexed thread is executed on the core of the processing unit, and wherein the multiplexed thread comprises: one or more time critical tasks; and a best effort task.