# US 10,503,517 B2 · Method for booting a heterogeneous system and presenting a symmetric core view

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- Number: US 10,503,517 B2
- Document ID: US10503517B2
- Status: Granted
- Kind: B2
- Application number: 15/672,254
- Filed: 2017-08-08
- Published: 2018-03-01
- Granted: 2019-12-10
- Earliest claimed: 2013-03-15
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Eliezer Weissmann; Rinat Rappoport; Michael Mishaeli; Hisham Shafi; Oron Lenz; Jason W. Brandt; Stephen A. Fischer; Bret L. Toll; Inder M. Sodhi; Alon Naveh; Ganapati N. Srinivasa; Ashish V. Choubal; Scott D. Hahn; David A. Koufaty; Russel J. Fenger; Gaurav Khanna; Eugene Gorbatov; Mishali Naik; Andrew J. Herdrich; Abirami Prabhakaran; Sanjeev S. Sahagirdar; Paul Brett; Paolo Narvaez; Andrew D. Henroid; Dheeraj R. Subbareddy
- Web page: https://patentgrep.com/patent/US10503517B2

## CPC

- G06F 9/4401: Bootstrapping (security arrangements therefor G06F21/57)
- G06F 9/45558: {Hypervisor-specific management and integration aspects}
- G06F 9/5077: {Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455)}
- G06F 9/5094: {where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

## Claims

### Claim 1

A processor comprising:
a first physical core having a first instruction set and a first power consumption level, to execute a thread at a first performance level;
a second physical core having a second instruction set and a second power consumption level, to execute a thread at a second performance level, the first and second cores being in a dynamic multi-core unit; and
a virtual-to-physical (V-P) mapping circuit coupled to the first and second physical cores, to map the first physical core to a system firmware interface via a virtual core and to hide the second processor core from the system firmware interface.

### Claim 2 (depends on 1)

The processor as in claim 1 further comprising a third physical core having the first instruction set and the first power consumption level, wherein the V-P mapping circuit is to map a first virtual core to the first physical core and to map a second virtual core to the third physical core, to allow a set of threads to be executed in parallel across the first and third physical processor cores.

### Claim 3 (depends on 2)

The processor as in claim 2 wherein the V-P mapping logic is to map the second virtual core to the second physical core transparently to the firmware interface in response to detected characteristics associated with the set of threads being executed.

### Claim 4 (depends on 3)

The processor as in claim 3 wherein the first power consumption level is lower than the second power consumption level.

### Claim 5 (depends on 4)

The processor as in claim 4 wherein the second performance level is higher than the first performance level.

### Claim 6 (depends on 5)

The processor as in claim 5 wherein the second physical core is made accessible to software by the V-P mapping circuit by mapping one or more of the virtual cores to the second physical core.

### Claim 7 (depends on 1)

The processor as in claim 1 wherein a single physical core of the processor acts as a bootstrap processor.

### Claim 8 (depends on 7)

The processor as in claim 7 wherein the first physical core acts as the bootstrap processor.

### Claim 9 (depends on 8)

The processor as in claim 8 wherein the bootstrap processor initializes the second physical core.

### Claim 10

A method comprising:
providing a set of one or more small physical processor cores;
providing at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores;
exposing a set of two or more small physical processor cores to a system firmware interface; and
hiding the at least one large physical processor core from the system firmware interface.

### Claim 11 (depends on 10)

The method as in claim 10 further comprising:
dynamically swapping a thread from a first small physical processor core to a large physical processor core, to allow the threads to be executed in on the large physical processor core, wherein the swapping is transparent to the thread.

### Claim 12 (depends on 10)

The method as in claim 10 further comprising:
nominating a small physical processor core from the set of small physical processor cores as a bootstrap processor;
initializing, by the bootstrap processor, each processor in the set of small physical cores; and
initializing, by the bootstrap processor the at least one large physical core.

### Claim 13 (depends on 12)

The method as in claim 12 wherein the small physical processor cores are exposed to the software through a default mapping between virtual processors and small physical processor cores.

### Claim 14 (depends on 13)

The method as in claim 13 wherein the at least one large physical processor core is hidden from the system firmware interface and made accessible to an operating system by transparently mapping one or more of the virtual cores to the large physical processor cores.

### Claim 15 (depends on 14)

The method as in claim 14 wherein the large physical processor is visible to an operating system having support for processor cores having multiple instruction sets.