# US 10,503,514 B2 · Method for implementing a reduced size register view data structure in a microprocessor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,514 B2 - Document ID: US10503514B2 - Status: Granted - Kind: B2 - Application number: 15/806,189 - Filed: 2017-11-07 - Published: 2018-03-01 - Granted: 2019-12-10 - Earliest claimed: 2013-03-15 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Mohammad Abdallah - Web page: https://patentgrep.com/patent/US10503514B2 ## CPC - G06F 9/3838: {Dependency mechanisms, e.g. register scoreboarding} - G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 9/3853: {of compound instructions} - G06F 9/3854: {Instruction completion, e.g. retiring, committing or graduating} - G06F 9/3858: {Result writeback, i.e. updating the architectural state or memory} - G06F 9/3863: {using multiple copies of the architectural state, e.g. shadow registers} - G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method of managing a reduced size register view data structure in a processor, where the method includes receiving an incoming instruction sequence using a global front end, grouping instructions from the incoming instruction sequence to form instruction blocks, populating a register view data structure, wherein the register view data structure stores register information references by the instruction blocks as a set of register templates, generating a set of snapshots of the register templates to reduce a size of the register view data structure, and tracking a state of the processor to handle a branch miss-prediction using the register view data structure in accordance with execution of the instruction blocks. ## Claims ### Claim 1 A method of managing a reduced size register view data structure in a processor, the method comprising: receiving an incoming instruction sequence using a global front end; grouping instructions from the incoming instruction sequence to form instruction blocks; populating a register view data structure, wherein the register view data structure stores register information references by the instruction blocks as a set of register templates; generating a set of snapshots of the register templates to reduce a size of the register view data structure; and tracking a state of the processor to handle a branch miss-prediction using the register view data structure in accordance with execution of the instruction blocks. ### Claim 2 (depends on 1) The method of claim 1, wherein the register view data structure, a source view data structure and an instruction view data structure are parts of a scheduler architecture of the processor. ### Claim 3 (depends on 1) The method of claim 1, further comprising: determining a last valid register template snapshot in response to branch misprediction. ### Claim 4 (depends on 1) The method of claim 1, further comprising: compressing the set of snapshots of the register templates by storing incremental changes between a subset of the set of snapshots. ### Claim 5 (depends on 1) The method of claim 1, further comprising: restoring a valid state for the processor by loading a valid register view data structure. ### Claim 6 (depends on 5) The method of claim 5, wherein the valid register view data structure is reconstructed from a valid register view snapshot. ### Claim 7 (depends on 1) The method of claim 1, wherein each register template stores inheritance vectors that define dependency and inheritance information referred to by a corresponding instructions block. ### Claim 8 A processor configured to implement a method of managing a reduced size register view data structure, the processor comprising: a set of execution units; a global front end to receive an incoming instruction sequence and to group instructions from the incoming instruction sequence to form instruction blocks; and a scheduler to schedule execution of the instruction blocks to the set of execution units, the scheduler including a register view data structure, the scheduler to populate a register view data structure, wherein the register view data structure stores register information references by the instruction blocks as a set of register templates, to generate a set of snapshots of the register templates to reduce a size of the register view data structure, and to track a state of the processor to handle a branch miss-prediction using the register view data structure in accordance with execution of the instruction blocks. ### Claim 9 (depends on 8) The processor of claim 8, wherein the register view data structure, a source view data structure and an instruction view data structure are parts of a scheduler architecture of the processor. ### Claim 10 (depends on 8) The processor of claim 8, wherein the scheduler is further configured to determine a last valid register template snapshot in response to branch misprediction. ### Claim 11 (depends on 8) The processor of claim 8, wherein the scheduler is further configured to compress the set of snapshots of the register templates by storing incremental changes between a subset of the set of snapshots. ### Claim 12 (depends on 8) The processor of claim 8, wherein the scheduler is further configured to restore a valid state for the processor by loading a valid register view data structure. ### Claim 13 (depends on 12) The processor of claim 12, wherein the valid register view data structure is reconstructed from a valid register view snapshot. ### Claim 14 (depends on 8) The processor of claim 8, wherein each register template stores inheritance vectors that define dependency and inheritance information referred to by a corresponding instructions block. ### Claim 15 A computer system configured to implement a method of managing a reduced size register view data structure, the computer system comprising: a memory to store a set of instructions; and a processor coupled to the memory, the processor including a set of execution units, a global front end to receive an incoming instruction sequence and to group instructions from the incoming instruction sequence to form instruction blocks, and a scheduler to schedule execution of the instruction blocks to the set of execution units, the scheduler including a register view data structure, the scheduler to populate a register view data structure, wherein the register view data structure stores register information references by the instruction blocks as a set of register templates, to generate a set of snapshots of the register templates to reduce a size of the register view data structure, and to track a state of the processor to handle a branch miss-prediction using the register view data structure in accordance with execution of the instruction blocks. ### Claim 16 (depends on 15) The computer system of claim 15, wherein the register view data structure, a source view data structure and an instruction view data structure are parts of a scheduler architecture of the processor. ### Claim 17 (depends on 15) The computer system of claim 15, wherein the scheduler is further configured to determine a last valid register template snapshot in response to branch misprediction. ### Claim 18 (depends on 15) The computer system of claim 15, wherein the scheduler is further configured to compress the set of snapshots of the register templates by storing incremental changes between a subset of the set of snapshots. ### Claim 19 (depends on 15) The computer system of claim 15, wherein the scheduler is further configured to restore a valid state for the processor by loading a valid register view data structure. ### Claim 20 (depends on 19) The computer system of claim 19, wherein the valid register view data structure is reconstructed from a valid register view snapshot.