# US 10,503,511 B2 · Circuit, system, and method for determining whether a branch instruction is predicted based on a capture range of a second instruction

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- Number: US 10,503,511 B2
- Document ID: US10503511B2
- Status: Granted
- Kind: B2
- Application number: 15/169,277
- Filed: 2016-05-31
- Published: 2016-09-22
- Granted: 2019-12-10
- Earliest claimed: 2007-10-23
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Hiroyuki Mizuno; Yoann Foucher
- Web page: https://patentgrep.com/patent/US10503511B2

## CPC

- G06F 9/3806: {using address prediction, e.g. return stack, branch history buffer}
- G06F 9/3004: {to perform operations on memory}
- G06F 9/30058: {Conditional branch instructions}
- G06F 9/30185: {according to one or more bits in the instruction, e.g. prefix, sub-opcode}
- G06F 9/30189: {according to execution mode, e.g. mode flag}
- G06F 9/323: {for indirect branch instructions}
- G06F 9/3802: {Instruction prefetching}
- G06F 9/382: {Pipelined decoding, e.g. using predecoding}
- G06F 9/3844: {using dynamic branch prediction, e.g. using branch history tables}
- G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A processor is provided for use with a memory having selectable memory areas. In an example, the processor includes a memory area selection circuit (MMU) to select one of the selectable memory areas, and an instruction fetch circuit to fetch a target instruction at an address from the selected memory area. The processor includes an execution circuit (Pipeline) to execute instructions from the instruction fetch circuit and to execute a first instruction for changing the selection by the MMU to a second selectable memory area. The Pipeline executes a branch instruction that points to a target instruction, where access to the target instruction depends on actual change of selection to the second memory area. The processor also includes a logic circuit to ensure fetch of the target instruction in response to the branch instruction after actual change of selection. Other circuits, devices, systems, apparatus, and processes are also disclosed.

## Claims

### Claim 1

A method of managing branch prediction, the method comprising:
initiating execution, by an execution circuit, of a first branch instruction pointing to a target instruction, wherein the target instruction is located in a first memory area;
detecting, by a logic circuit, execution of a first instruction, the first instruction changing a memory selection from a second memory area to the first memory area;
detecting, by the logic circuit, whether the first branch instruction is within a capture range of the first instruction, after detecting execution of the first instruction; and
disabling a branch prediction circuit, in response to detecting that the first branch instruction is within the capture range of the first instruction.

### Claim 2 (depends on 1)

The method of claim 1, further comprising executing, by the execution circuit, the first instruction.

### Claim 3 (depends on 1)

The method of claim 1, further comprising fetching, by an instruction fetch circuit, the target instruction.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
detecting that a second branch instruction is outside the capture range of the first instruction;
predicting, by the branch prediction circuit, branch behavior comprising a predicted target address of the second branch instruction, wherein the branch behavior is based on a branch target buffer;
fetching, by an instruction fetch circuit, a second instruction from the predicted target address; and
updating, by the branch prediction circuit, the branch target buffer in response to execution of the second branch instruction.

### Claim 5 (depends on 4)

The method of claim 4, further comprising suppressing updating of the branch target buffer in response to execution of the first branch instruction, in response to detecting that the first branch instruction is within the capture range of the first instruction.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first instruction is a store instruction.

### Claim 7 (depends on 1)

The method of claim 1, wherein detecting the execution of the first instruction comprises detecting a match between an instruction address of the first instruction and an address of a set of stored addresses.

### Claim 8 (depends on 1)

The method of claim 1, wherein detecting the execution of the first instruction comprises detecting that the first instruction comprises a particular store instruction code.

### Claim 9 (depends on 1)

The method of claim 1, wherein detecting the execution of the first instruction comprises detecting a store instruction code to a predetermined register in a memory area of a selection circuit.

### Claim 10 (depends on 1)

The method of claim 1, wherein the capture range comprises a predetermined number of instruction addresses.

### Claim 11 (depends on 1)

The method of claim 1, wherein the capture range comprises a predetermined number of instructions.

### Claim 12 (depends on 1)

The method of claim 1, wherein the capture range comprises a predetermined number of clock counts.

### Claim 13 (depends on 1)

The method of claim 1, wherein the first instruction comprises a qualifier for the first instruction.

### Claim 14 (depends on 13)

The method of claim 13, where the detecting of whether the first branch instruction is within the capture range of the first instruction is performed based on the qualifier.

### Claim 15 (depends on 1)

The method of claim 1, further comprising sending a mis-prediction signal initiating fetching the target instruction, in response to execution of the first branch instruction.

### Claim 16

An integrated circuit comprising:
an execution circuit operable to receive a first branch instruction that references a target instruction that is within a memory having a plurality of selectable areas;
a branch prediction circuit operable to determine branch prediction information for the first branch instruction;
a memory area selection unit operable to select between the plurality of selectable areas of the memory; and
a logic circuit operable to:
detect execution of a first instruction that causes the memory area selection unit to change between the plurality of selectable areas;
determine whether the first branch instruction is within a capture range of the first instruction; and
in response to determining that the first branch instruction is within the capture range of the first instruction, inhibit the branch prediction circuit from determining the branch prediction information.

### Claim 17 (depends on 16)

The integrated circuit of claim 16, wherein:
the execution circuit is further operable to receive a second branch instruction;
the branch prediction circuit is further operable to determine a second set of branch prediction information for the second branch instruction; and
the logic circuit is further operable to, when it is determined that the second branch instruction is beyond the capture range of the first instruction, permit the branch prediction circuit to determine the second set of branch prediction information for the second branch instruction.

### Claim 18 (depends on 16)

The integrated circuit of claim 16, wherein the first instruction is a store instruction.

### Claim 19 (depends on 16)

The integrated circuit of claim 16, wherein the capture range comprises a predetermined number of instruction addresses.