# US 10,503,510 B2 · SM3 hash function message expansion processors, methods, systems, and instructions

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- Number: US 10,503,510 B2
- Document ID: US10503510B2
- Status: Granted
- Kind: B2
- Application number: 14/142,745
- Filed: 2013-12-27
- Published: 2015-07-02
- Granted: 2019-12-10
- Earliest claimed: 2013-12-27
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Gilbert M. Wolrich; Vinodh Gopal; Kirk S. Yap; Wajdi K. Feghali; Sean Gulley
- Web page: https://patentgrep.com/patent/US10503510B2

## CPC

- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/30007: {to perform operations on data operands}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30038: {using a mask}
- G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00)
- H04L 9/0643: {Hash functions, e.g. MD5, SHA, HMAC or f9 MAC}
- H04L 2209/122: Hardware reduction or efficient architectures
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A processor includes a decode unit to receive an instruction to indicate a first source packed data operand and a second source packed data operand. The source operands each to include elements. The data elements to include information selected from messages and logical combinations of messages that is sufficient to evaluate: P1(Wj−16 XOR Wj−9 XOR (Wj−3<<<15)) XOR(Wj−13<<<7)XOR Wj−6 P1 is a permutation function, P1(X)=X XOR (X<<<15) XOR (X<<<23). Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6 are messages associated with a compression function of an SM3 hash function. XOR is an exclusive OR operation. <<< is a rotate operation. An execution unit coupled with the decode unit that is operable, in response to the instruction, to store a result packed data in a destination storage location. The result packed data to include a Wj message to be input to a round j of the compression function.

## Claims

### Claim 1

A processor comprising:
a plurality of packed data registers;
a decode unit to decode an instruction that is to indicate a first source packed data operand and to indicate a second source packed data operand, wherein the instruction has a field to explicitly specify a first packed data register of the plurality of packed data registers which is to store one of the first and second source packed data operands, the first and second source packed data operands each to include a plurality of data elements, the data elements of the first and second source packed data operands to include information selected from messages and logical combinations of messages associated with an SM3 hash function that is sufficient to evaluate:
P1(Wj−16 XOR Wj−9 XOR (Wj−3<<<15)) XOR (Wj−13<<<7) XOR Wj−6,
in which P1 is a permutation function P1(X)=X XOR (X<<<15) XOR (X<<<23), Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6 are messages associated with a compression function of the SM3 hash function, XOR is an exclusive OR operation, and <<< is a rotate operation, wherein said one of the first and second source packed data operands is to include a first data element at a first position in the first packed data register, the first data element to be equal to a logical combination of a subset of the messages Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6; and
an execution unit coupled with the decode unit, the execution unit operable, in response to the decode of the instruction, to store a result packed data in the first packed data register, the result packed data to include a Wj message to be input to a round j of the compression function of the SM3 hash function,
wherein the instruction implicitly indicates that the first packed data register is also to be used to store the result packed data, and
wherein the Wj message is to be stored at the first position in the first packed data register overwriting the logical combination of the subset of the messages Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6.

### Claim 2 (depends on 1)

The processor of claim 1, in which the decode unit is to decode the instruction in which the data elements of the first and second source packed data operands are to include a first subset of the messages Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6 and are to include the logical combination which is to be of a second different subset of the messages Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6, and wherein the result packed data is to include no more than three new messages for three new rounds.

### Claim 3 (depends on 2)

The processor of claim 2, in which the data elements of the first and second source packed data operands are to include the messages Wj−16, Wj−9, Wj−3, and the logical combination W*j−6 which is to be equal to (Wj−13<<<7) XOR Wj−6.

### Claim 4 (depends on 1)

The processor of claim 1, in which the decode unit is to decode the instruction in which the data elements of the first and second source packed data operands are to include information selected from messages and logical combinations of messages sufficient to evaluate:
P1(Wj−15 XOR Wj−8 XOR (Wj−2<<<15)) XOR (Wj−12<<<7) XOR Wj−5, in which Wj−15, Wj−8, Wj−2, Wj−12, and Wj−5 are messages associated with the compression function, and in which the execution unit is to store a Wj+1 message in the result packed data, the Wj+1 message to be input to a round j+1 of the compression function, and wherein the execution unit is to calculate the messages Wj and Wj+1 in parallel.

### Claim 5 (depends on 4)

The processor of claim 4, in which the data elements of the first and second source packed data operands are to include a first subset of the messages Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6 and the logical combination which is to be of a second different subset of the messages Wj−16, Wj−9, Wj−3, Wj−13, and W−6, and in which the data elements of the first and second source packed data operands are to include a first subset of the messages Wj−15, Wj−8, Wj−2, Wj−12, and Wj−5 and a second combination of a second different subset of the messages Wj−15, Wj−8, Wj−2, Wj−12, and Wj−5.

### Claim 6 (depends on 5)

The processor of claim 5, in which the data elements of the first and second source packed data operands are to include the messages Wj−16, Wj−9, Wj−3, Wj−15, Wj−8, Wj−2, and the logical combination W*j−6, and the second combination W*j−5, in which W*j−6 is to be equal to (Wj−13<<<7) XOR Wj−6, and in which W*j−5 is to be equal to (Wj−12<<<7) XOR Wj−5.

### Claim 7 (depends on 5)

The processor of claim 5, in which the execution unit is to store the Wj and Wj+1 messages over the logical combination and the second combination.

### Claim 8 (depends on 4)

The processor of claim 4, in which the data elements of the first and second source packed data operands are to include at least three pairs of messages from adjacent rounds selected from a pair Wj−2 and Wj−3, a pair Wj−5 and Wj−6, a pair Wj−8 and Wj−9, a pair Wj−12 and Wj−13, and a pair Wj−15 and Wj−16, and in which each of the at least three pairs of messages is to have its corresponding messages in a same source packed data operand.

### Claim 9 (depends on 4)

The processor of claim 4, in which the decode unit is to decode the instruction that is to indicate only the first and second source packed data operands as source operands, in which the first and second source packed data operands are each to be a 128-bit packed data operand and are each to have four 32-bit data elements, and in which the data elements of the first and second source packed data operands are to include six messages Wj−16, Wj−9, Wj−3, Wj−15, Wj−8,Wj−2, a first combination W*j−6 as the logical combination and a second combination W*j−5, in which W*j−6 is to be equal to (Wj−13<<<7) XOR Wj−6, and in which W*j−5 is to be equal to (Wj−12<<<7) XOR Wj−5.

### Claim 10 (depends on 1)

The processor of claim 1, in which the decode unit is to decode the instruction in which the data elements of the first and second source packed data operands are to include messages and logical combinations of messages sufficient to evaluate:
P1(Wj−14 XOR Wj−7 XOR (Wj−1<<<15)) XOR (Wj−11<<<7) XOR Wj−4,
in which Wj−14, Wj−7, Wj−1, Wj−11, and Wj−4 are messages associated with the compression function, and in which the execution unit is to store a Wj+2 message in the result packed data, the Wj+2 message to be input to a round j+2 of the compression function, and wherein the execution unit is to calculate the messages Wj, Wj+1, and Wj+2 in parallel.

### Claim 11 (depends on 1)

The processor of claim 1, wherein the result packed data is to include the message Wj−16.

### Claim 12 (depends on 1)

The processor of claim 1, wherein the result packed data is to include three new messages for three new rounds, but no more than the three new messages for the three new rounds.

### Claim 13

A method in a processor, the method comprising:
receiving an instruction, the instruction indicating a first source packed data operand and indicating a second source packed data operand, wherein a field of the instruction explicitly specifies an architectural packed data register of the processor which stores one of the first and second source packed data operands, the first and second source packed data operands each including a plurality of data elements, the data elements of the first and second source packed data operands including information selected from messages and logical combinations of messages that is sufficient to evaluate:
P1(Wj−16 XOR Wj−9 XOR (Wj−3<<<15)) XOR (Wj−13<<<7) XOR Wj−6,
in which P1 is a permutation function:
P1(X)=X XOR (X<<<15) XOR (X<<<23),
in which Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6 are messages associated with a compression function of an SM3 hash function, in which XOR is an exclusive OR operation, and in which <<< is a rotate operation, wherein said one of the first and second source packed data operands includes a first data element at a first position in the architectural packed data register, the first data element equal to a logical combination of a subset of the messages Wj−16, Wj−9, Wj−3, W−13, and Wj−6; and
storing a result packed data in the architectural packed data register the result packed data including a Wj message to be input to a round j of the compression function of the SM3 hash function,
wherein the instruction implicitly indicates that the architectural packed data register is also used to store the result packed data,
wherein the Wj message is stored at the first position in the architectural packed data register overwriting the logical combination of the subset of the messages Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6, and
wherein the result packed data also stores the message Wj−6.

### Claim 14 (depends on 13)

The method of claim 13, in which receiving comprises receiving the instruction in which the data elements of the first and second source packed data operands include a first subset of the messages Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6 and include the logical combination which is of a second different subset of the messages Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6.

### Claim 15 (depends on 14)

The method of claim 14, in which the data elements of the first and second source packed data operands include the messages Wj−16, Wj−9, Wj−3, and the logical combination W*j−6 which is equal to (Wj−13<<<7) XOR Wj−6.

### Claim 16 (depends on 13)

The method of claim 13, in which receiving comprises receiving the instruction in which the data elements of the first and second source packed data operands include messages and logical combinations of messages sufficient to evaluate:
P1(Wj−15 XOR Wj−8 XOR (Wj−2<<<15)) XOR (Wj−12<<<7) XOR Wj−5,
in which Wj−15, Wj−8, Wj−2, Wj−12, and Wj−5 are messages associated with the compression function, and in which the execution unit is to store a Wj+1 message in the result packed data, the Wj+1 message to be input to a round j+1 of the compression function, and wherein the messages Wj and Wj+1 are to be calculated in parallel.

### Claim 17 (depends on 16)

The method of claim 16, in which receiving comprises receiving the instruction in which the data elements of the first and second source packed data operands include a first subset of the messages Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6 and the logical combination which is of a second different subset of the messages Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6, and in which the data elements of the first and second source packed data operands include a first subset of the messages Wj−15, Wj−8, Wj−2, Wj−12, and Wj−5 and a second combination of a second different subset of the messages Wj−15, Wj−8, Wj−2, Wj−12, and Wj−5.

### Claim 18

A processor comprising:
a plurality of packed data registers;
a decode unit to decode an instruction, the instruction to indicate a first source packed data operand and to indicate a second source packed data operand, wherein the instruction has a field to explicitly specify a first packed data register of the plurality of packed data registers which is to store one of the first and second source packed data operands, the first and second source packed data operands each to include a plurality of data elements, the data elements of the first and second source packed data operands to include messages Wj−16, Wj−15, Wj−9, Wj−8, Wj−3, and Wj−2 associated with a compression function of an SM3 hash function, the data elements of the first and second source packed data operands to also include a first data element equal to a first combination W*j−6 which is to be equal to (Wj−13<<<7) XOR Wj−6, and a second data element equal to a second combination W*j−5 which is to be equal to (Wj−12<<<7) XOR Wj−5, where Wj−13, Wj−12, Wj−6, and Wj−5 are also messages associated with the compression function, wherein said one of the first and second source packed data operands is to include at least one of the first and second data elements at a first position in the first packed data register; and
an execution unit coupled with the decode unit, the execution unit operable, in response to the instruction, to store a result packed data in the first packed data register, the result packed data to include a Wj message to be input to a round j of the compression function, and a Wj+1 message to be input to a round j+1 of the compression function,
wherein the first packed data register is implicitly to be used to store the result packed data,
wherein the Wj message is to be stored at the first position in the first packed data register overwriting said one of the first and second data elements.

### Claim 19 (depends on 18)

The processor of claim 18, in which the execution unit is to store the Wj and Wj+1 messages over the first and second logical combinations W*j−6 and W*j−5.

### Claim 20 (depends on 18)

The processor of claim 18, in which the messages Wj−16 and Wj−15 are in a same source packed data operand, in which the messages Wj−9 and Wj−8 are in a same source packed data operand, and in which the messages Wj−3 and Wj−2 are in a same source packed data operand, and wherein the result packed data is to include the message Wj−16.

### Claim 21 (depends on 18)

The processor of claim 18, wherein the result packed data is to include no more than three new messages for three new rounds.

### Claim 22

A system to process instructions comprising:
an interconnect;
a processor coupled with the interconnect, the processor having a plurality of packed data registers, the processor to receive an instruction that is to indicate a first source packed data operand and to indicate a second source packed data operand, the instruction having a field to explicitly specify a first packed data register of the plurality of packed data registers which is to store one of the first and second source packed data operands, the first and second source packed data operands each to include a plurality of data elements, the data elements of the first and second source packed data operands to include information selected from messages and logical combinations of messages that is sufficient to evaluate:
P1(Wj−16 XOR Wj−9 XOR (Wj−3<<<15)) XOR (Wj−13<<<7) XOR
in which P1 is a permutation function:
P1(X)=X XOR (X<<<15) XOR (X<<<23),
in which Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6 are messages associated with a compression function of an SM3 hash function, in which XOR is an exclusive OR operation, and in which <<< is a rotate operation, wherein said one of the first and second source packed data operands is to include a first data element at a first position in the first packed data register, the first data element to be equal to a logical combination of a subset of the messages Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6, the processor operable, in response to the instruction, to store a result packed data in the first packed data register the result packed data to include a Wj message to be input to a round j of the compression function of the SM3 hash function, wherein the instruction is to implicitly indicate that the first packed data register is also to be used to store the result packed data, and wherein the Wj message is to be stored at the first position in the first packed data register overwriting the logical combination of the subset of the messages Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6; and
a dynamic random access memory (DRAM) coupled with the interconnect.

### Claim 23 (depends on 22)

The system of claim 22, in which the Wj message is to be stored over a logical combination of two messages.

### Claim 24

A processor comprising:
a plurality of packed data registers;
a decode unit to decode an instruction that is to indicate a first source packed data operand and to indicate a second source packed data operand, wherein the instruction has a field to explicitly specify a packed data register of the plurality of packed data registers which is to store one of the first and second source packed data operands, the first and second source packed data operands each to include a plurality of data elements, the data elements of the first and second source packed data operands to include information selected from messages and logical combinations of messages associated with an SM3 hash function that is sufficient to evaluate:
P1(Wj−16 XOR Wj−9 XOR (Wj−3<<<15)) XOR (Wj−13<<<7) XOR Wj−6,
in which P1 is a permutation function P1(X)=X XOR (X<<<15) XOR (X<<<23), Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6 are messages associated with a compression function of the SM3 hash function, XOR is an exclusive OR operation, and <<< is a rotate operation; and
an execution unit coupled with the decode unit, the execution unit operable, in response to the decode of the instruction, to store a result packed data in a destination storage location that is to be indicated by the instruction, the result packed data to include three new messages for three new rounds but no more than the three new messages for the three new rounds, the three new messages to include a Wj message to be input to a round j of the compression function of the SM3 hash function, and the result packed data to include the message Wj−16.

### Claim 25 (depends on 24)

The processor of claim 24, wherein said one of the first and second source packed data operands is to include a first data element at a first position in the packed data register, the first data element to be equal to a logical combination of a subset of the messages Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6, and wherein it is implicit to the instruction that the Wj message is to be stored over the logical combination in the packed data register.