# US 10,503,509 B2 · System and method for communication using a register management array circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,509 B2 - Document ID: US10503509B2 - Status: Granted - Kind: B2 - Application number: 15/282,444 - Filed: 2016-09-30 - Published: 2018-04-05 - Granted: 2019-12-10 - Earliest claimed: 2016-09-30 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Alexander Gendler; Eliezer Weissmann; Michael Mishaeli - Web page: https://patentgrep.com/patent/US10503509B2 ## CPC - G06F 9/30138: {Extension of register space, e.g. register cache} - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/30112: {comprising data of variable length} - G06F 9/3012: {Organisation of register space, e.g. banked or distributed register file} - G06F 9/50: Allocation of resources, e.g. of the central processing unit [CPU] - G06F 9/544: {Buffers; Shared memory; Pipes} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A system for communication using a register management array circuit is disclosed, including a processor, including a processing core, the processing core including a local core register, a register management array circuit coupled to the local core register, and a remote circuit coupled to the register management array circuit, the remote circuit including a remote register. The register management array circuit includes circuitry to cause the data in the local core register to match the data in the remote register. Methods and circuits are also disclosed. ## Claims ### Claim 1 A processor, comprising: a processing core, the processing core including a local core register; a remote circuit, the remote circuit including: a remote register to store data associated with one or more operational parameters of the processing core; and circuitry to control the one or more operational parameters of the processing core based on the data in the remote register; a register management array circuit, the register management array circuit including circuitry to cause data in the local core register to match the data in the remote register, wherein: the data in the local core register is to be written to the remote register upon receiving a write request from the processing core; and the data in the remote register is to be written to the local core register upon receiving a read request from the processing core. ### Claim 2 (depends on 1) The processor of claim 1, wherein the circuitry to cause the data in the local core register to match the data in the remote register includes circuitry to: receive, from the processing core, the write request including: the data to be written from the local core register to the remote register; and a logical address of the remote register; identify, based on the logical address of the remote register, a physical address of the remote register; and write, based on the identified physical address of the remote register, the data to the remote register. ### Claim 3 (depends on 2) The processor of claim 2, wherein: the register management array circuit further includes: a register management array control circuit coupled to a register management array; the register management array to include: a plurality of logical address index values; and a plurality of physical addresses, each associated with a respective one of the plurality of the logical address index values; and the circuitry to identify, based on the logical address of the remote register, a physical address of the remote register includes circuitry in the register management array control circuit to read from the register management array, a physical address corresponding to the logical address of the remote register. ### Claim 4 (depends on 1) The processor of claim 1, wherein the circuitry to cause the data in the local core register to match the data in the remote register includes circuitry to: receive, from the processing core, the read request including a logical address of the remote register; identify, based on the logical address of the remote register, a physical address of the remote register; read, based on the identified physical address of the remote register, the data from the remote register; and write the data to the local core register. ### Claim 5 (depends on 2) The processor of claim 2, wherein the circuitry to receive, from the processing core, the write request, includes circuitry to receive a request from the processing core through a parallel event bus. ### Claim 6 (depends on 2) The processor of claim 2, wherein the circuitry to write, based on the identified physical address of the remote register, the data to the remote register includes circuitry to send the data to the remote register through a general purpose sideband interface. ### Claim 7 (depends on 1) The processor of claim 1, wherein the register management array circuit is located in a core periphery of the processing core. ### Claim 8 (depends on 1) The processor of claim 1, wherein the remote circuit further includes a power management circuit, the power management circuit including circuitry to control a frequency or a voltage of the processing core based on the data in the remote register. ### Claim 9 A method, comprising: writing, by a processing core, data to be written to a remote register to a local core register in the processing core, wherein: the remote register is in a remote circuit; and the remote circuit is to control one or more operational parameters of the processing core based on data in the remote register; sending a write request to a register management array circuit coupled to the local core register, the write request including a logical address of the remote register; identifying, based on the logical address of the remote register, a physical address of the remote register; and writing, based on the identified physical address of the remote register, the data to the remote register. ### Claim 10 (depends on 9) The method of claim 9, wherein identifying, based on the logical address of the remote register, a physical address of the remote register includes reading, from a register management array, the physical address of the remote register using the logical address of the remote register as an index value for the register management array. ### Claim 11 (depends on 9) The method of claim 9, further comprising, setting, in a dirty bit register, a dirty bit indicating that a write to the remote register is in progress. ### Claim 12 (depends on 9) The method of claim 9, wherein, writing the data to the remote register includes writing a plurality of segments of the data through a general purpose sideband interface. ### Claim 13 (depends on 12) The method of claim 12, further comprising: determining that fewer than all of the plurality of data segments have been written to the remote register; and based on the determination that fewer than all of the plurality of segments of the data have been written to the remote register, writing another one of the plurality of segments of the data. ### Claim 14 (depends on 13) The method of claim 13, further comprising: determining, subsequent to writing another one of the plurality of segments of data, that all of plurality of segments of the data have been written to the remote register; and based on the determination that all of the plurality segments of the data have been written to the remote register, unsetting a dirty bit indicating that a write is in progress to the remote register. ### Claim 15 A register management array circuit, comprising: a first interface to communicate with a processing core, the processing core including a local core register; a second interface to communicate with a remote circuit, the remote circuit including: a remote register to store data associated with one or more operational parameters of the processing core; and circuitry to control the one or more operational parameters of the processing core based on the data in the remote register; and circuitry to cause data in the local core register to match the data in the remote register, wherein: the data in the local core register is to be written to the remote register upon receiving a write request from the processing core; and the data in the remote register is to be written to the local core register upon receiving a read request from the processing core. ### Claim 16 (depends on 15) The register management array circuit of claim 15, wherein the circuitry to cause the data in the local core register to match the data in the remote register includes circuitry to: receive, from the processing core, the write request to include: the data to be written from the local core register to the remote register; and a logical address of the remote register; identify, based on the logical address of the remote register, a physical address of the remote register; and write, based on the identified physical address of the remote register, the data to the remote register. ### Claim 17 (depends on 16) The register management array circuit of claim 16, further comprising: a register management array to include: a plurality of logical address index values; and a plurality of physical addresses associated with one of the plurality of the logical address index value; and wherein the circuitry to identify, based on the logical address of the remote register, a physical address of the remote register includes circuitry to read, from the register management array, a physical address corresponding to the logical address of the remote register. ### Claim 18 (depends on 15) The register management array circuit of claim 15, wherein the circuitry to cause the data in the local core register to match the data in the remote register includes circuitry to: receive, from the processing core, the read request including a logical address of the remote register; identify, based on the logical address of the remote register, a physical address of the remote register; read, based on the identified physical address of the remote register, the data from the remote register; and write the data to the local core register. ### Claim 19 (depends on 16) The register management array circuit of claim 16, wherein the circuitry to receive, from the processing core, the write request, includes circuitry to receive a request from the processing core through a parallel event bus. ### Claim 20 (depends on 16) The register management array circuit of claim 16, wherein the circuitry to write, based on the identified physical address of the remote register, the data to the remote register includes circuitry to send the data to the remote register through a general purpose sideband interface. ### Claim 21 (depends on 15) The register management array circuit of claim 15, wherein the register management array circuit is located in a core periphery of the processing core.