# US 10,503,504 B2 · Event-driven design simulation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,504 B2 - Document ID: US10503504B2 - Status: Granted - Kind: B2 - Application number: 15/399,982 - Filed: 2017-01-06 - Published: 2017-09-07 - Granted: 2019-12-10 - Earliest claimed: 2016-03-04 - Assignees: Montana Systems Inc. - Applicants: Montana Systems Inc. - Inventors: Vivian Chou; Julien Lamoureux; Sherman Lee - Web page: https://patentgrep.com/patent/US10503504B2 ## CPC - G06F 9/3001: {Arithmetic instructions} - G06F 9/30029: {Logical and Boolean instructions, e.g. XOR, NOT} - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/3005: {to perform operations for flow control} - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/3802: {Instruction prefetching} - G06F 9/3838: {Dependency mechanisms, e.g. register scoreboarding} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 9/3885: {using a plurality of independent parallel functional units} - G06F 12/023: {Free address space management} - G06F 30/33: Design verification, e.g. functional simulation or model checking - G06F 30/3308: using simulation - G06F 30/331: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation - G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - G06F 2212/251: Local memory within processor subsystem - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A simulation system that includes a simulation accelerator that uses parallel processing to accelerate the simulation of register transfer level codes (RTLs) while minimizing memory access latency is disclosed. The accelerator has an array of parallel computing resources. The simulation accelerator receives compiled RTLs in which the components of the design are mapped to instructions. The instructions are divided into groups, in which instructions belonging to a same group are logically independent of each other. The simulation accelerator fetches instructions and data for processing by the parallel computing resources for one group of instructions at a time. ## Claims ### Claim 1 A simulation system configured to test a design by operating a testbench for the design, the simulation system comprising: a simulation storage; a simulation processor configured to (i) transport compiled design data from a host computing system to the simulation storage, the compiled design data comprising compiled register transfer levels (RTLs) of the design and compiled models of the testbench and (ii) execute the compiled models to generate stimulus for testing the compiled RTLs; and a simulation accelerator configured to execute the compiled RTLs by using the stimulus generated by the simulation processor as input, wherein the compiled RTLs comprise instructions that are executable at a plurality of hardware computing resources in the simulation accelerator, wherein the instructions are divided into a plurality of groups of instructions, wherein the instructions of each group of instructions are distributed to the plurality of hardware computing resources to be executed in parallel and in any order. ### Claim 2 (depends on 1) The simulation system of claim 1, wherein the simulation processor is operating an operating system for managing file transfer between the simulation system and the host computing system. ### Claim 3 (depends on 1) The simulation system of claim 1, wherein each instruction belonging to a group of instructions is logically and temporally independent of any other instruction belonging to the group. ### Claim 4 (depends on 1) The simulation system of claim 1, wherein the host computing system compiles a set of source files containing the testbench and the design into the compiled design data. ### Claim 5 (depends on 1) The simulation system of claim 1, wherein the simulation processor and the simulation accelerator exchange data over a first communications medium, wherein the simulation system and the host computing system exchange data over a second communications medium that has higher latency than the first communications medium. ### Claim 6 (depends on 1) The simulation system of claim 1, wherein the simulation processor and the simulation storage exchange data over a first communications medium, wherein the simulation system and the host computing system exchange data over a second communications medium that has higher latency than the first communications medium. ### Claim 7 (depends on 1) The simulation system of claim 1, wherein the compiled models comprise data for the simulation processor and instructions for the simulation accelerator, wherein the simulation accelerator is configured to execute the instructions from the compiled RTLs and the instructions from the compiled models. ### Claim 8 An integrated circuit (IC) configured to test a design by operating a testbench for the design, the IC comprising: a simulation processor configured to (i) retrieve compiled design data from a host computing system, the compiled design data comprising compiled register transfer levels (RTLs) of the design and compiled models of the testbench and (ii) execute the compiled models to generate stimulus for testing the compiled RTLs; and a simulation accelerator configured to execute the compiled RTLs by using the stimulus generated by the simulation processor as input, wherein the compiled RTLs comprise instructions that are executable at a plurality of hardware computing resources in the simulation accelerator, wherein the instructions are divided into a plurality of groups of instructions, wherein the instructions of each group of instructions are distributed to the plurality of hardware computing resources to be executed in parallel and in any order. ### Claim 9 (depends on 8) The IC of claim 8, wherein the simulation processor is operating an operating system for managing file retrieval from the host computing system. ### Claim 10 (depends on 8) The IC of claim 8, wherein each instruction belonging to a group of instructions is logically and temporally independent of any other instruction belonging to the group. ### Claim 11 (depends on 8) The IC of claim 8, wherein the host computing system compiles a set of source files containing the testbench and the design into the compiled design data. ### Claim 12 (depends on 8) The IC of claim 8, wherein the simulation processor and the simulation accelerator exchange data over a first communications medium, wherein the simulation system and the host computing system exchange data over a second communications medium that has higher latency than the first communications medium. ### Claim 13 (depends on 8) The IC of claim 8, wherein the compiled models comprise data for the simulation processor and instructions for the simulation accelerator, wherein the simulation accelerator is configured to execute the instructions from the compiled RTLs and the instructions from the compiled models. ### Claim 14 A method for testing a design by operating a testbench for the design, the method comprising: executing an operating system at a simulation processor; using the operating system to retrieve compiled design data from a host computing system to a simulation storage, the compiled design data comprising compiled register transfer levels (RTLs) of the design and compiled models of the testbench, wherein the compiled RTLs comprise instructions that are executable at a plurality of hardware computing resources in a simulation accelerator, wherein the instructions are divided into a plurality of groups of instructions; executing the compiled models at the simulation processor to generate stimulus for testing the compiled RTLs; and executing, at the simulation accelerator, the compiled RTLs by using the stimulus generated by the simulation processor as input, wherein the instructions of each group of instructions of the compiled RTLs are distributed to the plurality of hardware computing resources to be executed in parallel and in any order. ### Claim 15 (depends on 14) The method of claim 14, wherein each instruction belonging to a group of instructions is logically and temporally independent of any other instruction belonging to the group. ### Claim 16 (depends on 14) The method of claim 14, wherein the host computing system compiles a set of source files containing the testbench and the design into the compiled design data. ### Claim 17 (depends on 14) The method of claim 14, wherein the simulation processor and the simulation accelerator exchange data over a first communications medium, wherein the simulation system and the host computing system exchange data over a second communications medium that has higher latency than the first communications medium. ### Claim 18 (depends on 14) The method of claim 14, wherein the simulation processor and the simulation storage exchange data over a first communications medium, wherein the simulation system and the host computing system exchange data over a second communications medium that has higher latency than the first communications medium. ### Claim 19 (depends on 14) The method of claim 14, wherein the compiled models comprise data for the simulation processor and instructions for the simulation accelerator, the method further comprising executing the instructions from the compiled RTLs and the instructions from the compiled models at the simulation accelerator.