# US 10,503,477 B2 · Galois field pipelined multiplier with polynomial and beta input passing scheme

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- Number: US 10,503,477 B2
- Document ID: US10503477B2
- Status: Granted
- Kind: B2
- Application number: 15/836,491
- Filed: 2017-12-08
- Published: 2019-06-13
- Granted: 2019-12-10
- Earliest claimed: 2017-12-08
- Assignees: Exten Technologies, Inc.
- Applicants: EXTEN Technologies, Inc.
- Inventors: Daniel B. Reents; Ashwin Kamath
- Web page: https://patentgrep.com/patent/US10503477B2

## CPC

- G06F 7/724: {Finite field arithmetic (for error detection or correction in general H03M13/00, in computers G06F11/10)}
- G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}
- H03M 13/158: {Finite field arithmetic processing}
- H03M 13/373: {with erasure correction and erasure determination, e.g. for packet loss recovery or setting of erasures for the decoding of Reed-Solomon codes}
- H03M 13/617: {Polynomial operations, e.g. operations related to generator polynomials or parity-check polynomials}
- H03M 13/6516: {Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields}
- G06F 2211/1057: Parity-multiple bits-RAID6, i.e. RAID 6 implementations
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

The disclosure provides a very flexible mechanism for a storage controller to create RAID stripes and to re-create corrupted stripes when necessary using the erasure coding scheme. Typically, this is known as a RAID 6 implementation/feature. The erasure code calculations are generated using the Galois Multiplication hardware and the system controller can pass any polynomial into the hardware on a per stripe calculation basis. The polynomial value is passed to the hardware via an input descriptor field. The descriptor controls the entire computation process.

## Claims

### Claim 1

A system for performing a computation on a multiplier, comprising:
a load pointer to direct a 8-bit data in bus to a correct multiplier block of a series of multipliers in a round robin fashion;
the series of multipliers adapted to produce a series of 8 bit results, wherein the correct multiplier block is adapted to produce an individual 8 bit multiplier result based on the 8-bit data in bus; and
a result pointer that selects the individual 8 bit multiplier result from the correct multiplier block result for presentation on an output bus.

### Claim 2 (depends on 1)

The system of claim 1, wherein the series of multipliers includes a plurality of multipliers in parallel with each other.

### Claim 3 (depends on 1)

The system of claim 1, wherein the series of multipliers use a polynomial select value and a beta value.

### Claim 4 (depends on 3)

The system of claim 3, wherein the system is adapted to receive a descriptor.

### Claim 5 (depends on 4)

The system of claim 4, wherein the descriptor includes a polynomial select value and a beta value.

### Claim 6 (depends on 5)

The system of claim 5, wherein the beta value define an 8-bit constant value to be multiplied by the 8-bit data.

### Claim 7 (depends on 6)

The system of claim 6, wherein the descriptor includes a source of the 8-bit data.

### Claim 8 (depends on 7)

The system of claim 7, wherein the descriptor includes a P buffer.

### Claim 9 (depends on 8)

The system of claim 8, wherein the descriptor includes a Q buffer.

### Claim 10 (depends on 1)

The system of claim 1, wherein the series of multipliers is a Galois Field multiplier.

### Claim 11 (depends on 10)

The system of claim 10, wherein the series of multipliers uses a Linear Feedback Shift Register.

### Claim 12 (depends on 11)

The system of claim 11, wherein the series of multipliers are implemented in a 9 instance deep×32 instance wide arrangement.

### Claim 13 (depends on 1)

The system of claim 1, wherein the system resides in an IRAY node.