# US 10,503,474 B2 · Methods and instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition

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- Number: US 10,503,474 B2
- Document ID: US10503474B2
- Status: Granted
- Kind: B2
- Application number: 14/986,349
- Filed: 2015-12-31
- Published: 2017-07-06
- Granted: 2019-12-10
- Earliest claimed: 2015-12-31
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Srinivas Lingam; Seok-Jun Lee; Manish Goel
- Web page: https://patentgrep.com/patent/US10503474B2

## CPC

- G06F 7/523: Multiplying only
- G06F 7/50: Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence)
- G06F 7/5324: {partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition without a barrel shifter. Illustrative instructions include operations that include receiving a first 32-bit operand, receiving a second 32-bit operand, shifting the second 32-bit operand right 16 or 15 bits to obtain a shifted second 32-bit operand, and adding the shifted second 32-bit operand and the first 32-bit operand to generate a 32-bit sum.

## Claims

### Claim 1

A method of performing a multiplication of a first signed 32-bit operand and a second signed 32-bit operand using 32-bit architecture, the method comprising:
performing, by a 16-bit multiplier, a signed multiplication of the first 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a first 32-bit product;
performing, by the 16-bit multiplier, an unsigned multiplication of the last 16 bits of the first signed 32-bit operand and the first 16 bits of the second signed 32-bit operand, to generate a second 32-bit product;
adding, by an adder, the first 32-bit product to the second 32-bit product, to generate a first 32-bit sum;
performing, by the 16-bit multiplier, an unsigned multiplication of the last 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a third 32-bit product;
shifting the third 32-bit product right 16 bits and filling the first 16 bit positions with zeroes, to generate a shifted third 32-bit product;
adding, by the adder, the shifted third 32-bit product and the first 32-bit sum, to generate a second 32-bit sum;
performing, by the 16-bit multiplier, a signed multiplication of the first 16 bits of the first signed 32-bit operand and the first 16 bits of the second signed 32-bit operand, to generate a fourth 32-bit product;
shifting the second 32-bit sum right 15 bits and filling the first 15 bit positions with a value of the second 32-bit sum, to generate a shifted second 32-bit sum; and
adding the shifted second 32-bit sum and the fourth 32-bit product, to generate a product of the first and second signed 32-bit operands.

### Claim 2 (depends on 1)

The method of claim 1, wherein adding the first 32-bit product to the second 32-bit product is performed without shifting the first 32-bit product or the second 32-bit product.

### Claim 3 (depends on 1)

The method of claim 1, wherein adding the first 32-bit product to the second 32-bit product is performed without shifting the first 32-bit product or the second 32-bit product.

### Claim 4 (depends on 1)

The method of claim 1, further comprising performing loop execution by an instruction loop buffer.

### Claim 5

A processor to multiply a first signed 32-bit operand by a second signed 32-bit operand, the processor comprising:
a load store unit to load the first signed 32-bit operand and to load the second signed 32-bit operand;
a butterfly/adder;
a 16-bit multiplier;
a program controller; and
a memory coupled to the program controller, the memory storing instructions;
wherein, in response to at least one instruction of the instructions, the 16-bit multiplier is configured to:
perform a signed multiplication of the first 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a first 32-bit product; and
perform a signed multiplication of the last 16 bits of the first signed 32-bit operand and the first 16 bits of the second signed 32-bit operand, to generate a second 32-bit product;
wherein the butterfly/adder is configured to add the first 32-bit product to the second 32-bit product, to generate a first 32-bit sum;
wherein the 16-bit multiplier is configured to perform an unsigned multiplication of the last 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a third 32-bit product;
wherein the program controller is configured to execute a first single instruction of the instructions, that comprises respective opcode fields for the load store unit, the butterfly/adder, and the 16-bit multiplier; and
wherein the butterfly/adder opcode field controls the butterfly/adder to shift the third 32-bit product right by a fixed number of bits, wherein the fixed number of bits is 16 bits; and
fill the first 16 bit positions with zeroes, to generate a shifted third 32-bit product, wherein the first single instruction is a shift-right add signed/signed instruction or a shift-right add signed/unsigned instruction.

### Claim 6 (depends on 5)

The processor of claim 5, wherein:
the butterfly/adder is further configured to add the shifted third 32-bit product and the first 32-bit sum, to generate a second 32-bit sum;
the 16-bit multiplier is further configured to perform a signed multiplication of the first 16 bits of the first signed 32-bit operand and the first 16 bits of the second signed 32-bit operand, to generate a fourth 32-bit product; and
the program controller further is configured to execute a second single instruction that:
shifts the second 32-bit sum right 15 bits and fill the first 15 bit positions with a value of a sign bit of the second 32-bit sum, to generate a shifted second 32-bit sum; and
adds the shifted second 32-bit sum and the fourth 32-bit product, to generate a product of the first and second signed 32-bit operands.

### Claim 7 (depends on 5)

The processor of claim 5, wherein shifting the third 32-bit product right by the fixed number of bits is performed without a barrel shifter.

### Claim 8 (depends on 5)

The processor of claim 5, wherein the processor comprises an application specific integrated processor (ASIP) core, wherein the ASIP core comprises the load store unit, the butterfly/adder, the program controller and the 16-bit multiplier.

### Claim 9 (depends on 8)

The processor of claim 8, further comprising an instruction loop buffer for loop execution.

### Claim 10 (depends on 8)

The processor of claim 8, wherein the processor comprises a local bus coupled to the ASIP core, wherein an instruction word of the instructions has a width less than or equal to twice a width of the local bus.

### Claim 11 (depends on 5)

The processor of claim 5, wherein the butterfly/adder is an arithmetic logic unit (ALU) arranged to compute vector operations.

### Claim 12 (depends on 5)

The processor of claim 5, wherein an instruction word of the instructions has a width of 32 bits.

### Claim 13 (depends on 5)

The processor of claim 5, wherein adding the first 32-bit product to the second 32-bit product is performed without shifting the first 32-bit product or the second 32-bit product.

### Claim 14 (depends on 5)

The processor of claim 5, wherein the processor does not contain a barrel shifter.

### Claim 15

A processor to multiply a first signed 32-bit operand by a second signed 32-bit operand, the processor comprising:
local twiddle read only memory (ROM) storing constants for computation; and
an application specific integrated processor (ASIP) core, comprising:
a load store unit to load the first signed 32-bit operand and to load the second signed 32-bit operand;
a butterfly/adder;
a 16-bit multiplier;
an address register;
a step register; and
a program controller; and
a memory coupled to the program controller, the memory storing instructions;
wherein the 16-bit multiplier is configured to:
perform a signed multiplication of the first 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a first 32-bit product; and
perform a signed multiplication of the last 16 bits of the first signed 32-bit operand and the first 16 bits of the second signed 32-bit operand, to generate a second 32-bit product;
wherein the butterfly/adder is configured to add the first 32-bit product to the second 32-bit product, to generate a first 32-bit sum; and
wherein the 16-bit multiplier is configured to performing an unsigned multiplication of the last 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a third 32-bit product; and
wherein the program controller is configured to execute a first single instruction of the instructions, that:
shifts the third 32-bit product right by a fixed number of bits, wherein the fixed number of bits is 16 bits; and
fills the first 16 bit positions with zeroes, to generate a shifted third 32-bit product.

### Claim 16 (depends on 15)

The processor of claim 15, wherein the ASIP core further comprises a data register file comprising a set of data registers holding data for the load store unit, the 16-bit multiplier, and the butterfly/adder.

### Claim 17 (depends on 15)

The processor of claim 15, wherein the ASIP core further comprises:
a plurality of address registers coupled to the load store unit;
a plurality of step registers coupled to the load store unit; and
an address mask register coupled to the load store unit.

### Claim 18 (depends on 17)

The processor of claim 17, wherein the plurality of address registers are non-orthogonal to the load store unit, the 16-bit multiplier, and the butterfly/adder.

### Claim 19

A processor to multiply a first signed 32-bit operand by a second signed 32-bit operand, the processor comprising:
local twiddle read only memory (ROM) storing constants for computation; and
an application specific integrated processor (ASIP) core comprising:
a load store unit to load the first signed 32-bit operand and to load the second signed 32-bit operand;
a butterfly/adder;
a 16-bit multiplier; and
a program controller;
a block coupled to the ASIP core, the block, comprising:
core ROM;
a single port static random access memory (SRAM);
an arbiter; and
a cyclic redundancy check (CRC) and discrete Fourier transform (DFT); and
a memory coupled to the program controller, the memory storing instructions;
wherein the 16-bit multiplier is configured to:
perform a signed multiplication of the first 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a first 32-bit product; and
perform a signed multiplication of the last 16 bits of the first signed 32-bit operand and the first 16 bits of the second signed 32-bit operand, to generate a second 32-bit product;
wherein the butterfly/adder is configured to add the first 32-bit product to the second 32-bit product, to generate a first 32-bit sum;
wherein the 16-bit multiplier is configured to performing an unsigned multiplication of the last 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a third 32-bit product; and
wherein the program controller is configured to execute a first single instruction of the instructions, that:
shifts the third 32-bit product right by a fixed number of bits, wherein the fixed number of bits is 16 bits; and
fills the first 16 bit positions with zeroes, to generate a shifted third 32-bit product.

### Claim 20

A processor to multiply a first signed 32-bit operand by a second signed 32-bit operand, the processor comprising:
local twiddle read only memory (ROM) storing constants for computation; and
an application specific integrated processor (ASIP) core comprising:
a load store unit to load the first signed 32-bit operand and to load the second signed 32-bit operand;
a butterfly/adder;
a 16-bit multiplier; and
a program controller;
command registers coupled to the ASIP core;
command and switch control coupled to the command registers;
a co-processor slave interface coupled to the command and switch control, the co-processor slave interface coupled to a central processing unit (CPU); and
a memory coupled to the program controller, the memory storing instructions;
wherein the 16-bit multiplier is configured to:
perform a signed multiplication of the first 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a first 32-bit product; and
perform a signed multiplication of the last 16 bits of the first signed 32-bit operand and the first 16 bits of the second signed 32-bit operand, to generate a second 32-bit product;
wherein the butterfly/adder is configured to add the first 32-bit product to the second 32-bit product, to generate a first 32-bit sum;
wherein the 16-bit multiplier is configured to performing an unsigned multiplication of the last 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a third 32-bit product; and
wherein the program controller is configured to execute a first single instruction of the instructions, that:
shifts the third 32-bit product right by a fixed number of bits, wherein the fixed number of bits is 16 bits; and
fills the first 16 bit positions with zeroes, to generate a shifted third 32-bit product.