# US 10,503,439 B2 · Memory device and operating method including a partial program operation and a partial erase operation thereof

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- Number: US 10,503,439 B2
- Document ID: US10503439B2
- Status: Granted
- Kind: B2
- Application number: 16/159,287
- Filed: 2018-10-12
- Published: 2019-02-14
- Granted: 2019-12-10
- Earliest claimed: 2016-04-11
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Hee Youl Lee; Ji Ho Park
- Web page: https://patentgrep.com/patent/US10503439B2

## CPC

- G11C 16/10: Programming or data input circuits
- G06F 3/0614: {Improving the reliability of storage systems}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

There are provided a memory device and an operating method thereof. A memory device may include a memory block, peripheral circuits, and a control logic. The memory block may include a plurality of pages arranged in a vertical direction on a substrate. The peripheral circuits may perform a program operation on a selected page. The control logic may control the peripheral circuits to perform a first partial program operation of sequentially programming some of the pages up to a first page. The control logic may perform a first partial erase operation of erasing the other non-programmed pages. The control logic may perform a second partial program operation of partially programming the pages on which the first partial erase operation has been performed.

## Claims

### Claim 1

A method of operating a memory device including a string coupled between a source line and a bit line, the method comprising:
programming an Nth memory cell from the bit line in the string;
programming an Mth memory cell from the source line after the Nth memory cell from the bit line is programmed in the string;
erasing memory cells coupled between the Nth memory cell from the bit line and the Mth memory cell from the source line after the Mth memory cell from the source line is programmed; and
programming the erased memory cells,
wherein N and M are positive integers.

### Claim 2 (depends on 1)

The method of claim 1, wherein the Nth memory cell from the bit line is programmed by applying a program voltage to a word line coupled to the Nth memory cell from the bit line, and applying a pass voltage to word lines coupled to remaining memory cells, and the Mth memory cell from the source line is programmed by applying a program voltage to a word line coupled to the Mth memory cell from the source line, and applying the pass voltage to word lines coupled to remaining memory cells.

### Claim 3 (depends on 1)

The method of claim 1, wherein when the memory cells coupled between the Nth memory cell from the bit line and the Mth memory cell from the source line are erased, the Nth memory cell from the bit line and the Mth memory cell from the source line are not erased.

### Claim 4

A method of operating a memory device including a plurality of memory cells coupled between a source line and a bit line, the method comprising:
performing a first program operation on memory cells relatively closer to the bit lines and memory cells relatively closer to the source line, respectively, among the plurality of memory cells;
performing a first erase operation on memory cells, among the plurality of memory cells, except the memory cells on which the first program operation is performed;
performing a second program operation on memory cells among the memory cells on which the first erase operation is performed;
performing a second erase operation on memory cells, among the plurality of memory cells, except the memory cells on which the first program operation or the second program operation are performed; and
performing a third program operation on memory cells among the memory cells on which the second erase operation is performed.

### Claim 5 (depends on 4)

The method of claim 4, wherein when the third program operation is performed a third erase operation is performed on memory cells, among the plurality of memory cells, except the memory cells on which the first program operation, the second program operation, or the third program operation are performed.

### Claim 6

A method of operating a memory device including a plurality of pages coupled between a source line and a bit line, the method comprising:
programming an Nth page relatively close to the source line and an Nth page relatively close to the bit line, respectively, among the plurality of pages;
erasing pages between the Nth pages; and
programming the pages erased between the Nth pages,
wherein N is a positive integer.

### Claim 7 (depends on 6)

The method of claim 6, wherein each of the pages includes a plurality of memory cells coupled to a same word line.