# US 10,503,434 B2 · Scalable low-latency storage interface

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- Number: US 10,503,434 B2
- Document ID: US10503434B2
- Status: Granted
- Kind: B2
- Application number: 15/485,877
- Filed: 2017-04-12
- Published: 2018-10-18
- Granted: 2019-12-10
- Earliest claimed: 2017-04-12
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Edward McGlaughlin; Yves Tchapda; Stephen Marshall; Samuel Bradshaw; Niels Reimers
- Web page: https://patentgrep.com/patent/US10503434B2

## CPC

- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 13/161: {with latency improvement}
- G06F 13/1673: {using buffers}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F 12/0238: {Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory}
- G06F 2212/1024: Latency reduction
- G06F 2212/202: Non-volatile memory
- G06F 2212/205: Hybrid memory, e.g. using both volatile and non-volatile memory
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F 2213/0026: PCI express
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems and methods are disclosed, including a host interface circuit configured to control communication between a set of virtual functions (VFs) and a media management system (MMS). The host interface circuit can consolidate commands from the set of VFs, dynamically allocate write buffers (WBs) from a set of available WBs to the set of VFs using the commands, and manage WB access for the set of VFs and provide write data to the MMS using the allocated WBs. For each VF in the set of VFs, the host interface circuit can manage a submission queue (SQ) for a respective VF from the set of VFs, receive a command from the respective VF, including one or more submission queue entries (SQEs), and coordinate the one or more received SQEs with allocated WBs.

## Claims

### Claim 1

A system comprising:
a host interface circuit configured to control communication between a set of virtual functions (VFs) and a media management system (MMS), the host interface circuit including:
a command queue manager circuit configured to consolidate commands from the set of VFs, to dynamically allocate write buffers (WBs) from a set of available WBs to the set of VFs using the commands, and to provide commands to the MMS;
for each VF in the set of VFs:
a VF submission queue circuit configured to manage a submission queue (SQ) for a respective VF from the set of VFs, and to receive a command from the respective VF, including one or more submission queue entries (SQEs); and
a VF write buffer list (WBL) circuit configured to manage a list of pending writes for the respective VF and to coordinate the one or more received SQEs with allocated WBs; and
a WB access circuit configured to manage WB access for the set of VFs and to provide write data to the MMS,
wherein the host interface circuit is configured to allocate a first plurality WBs to receive multiple logical blocks of data of a first SQE, to receive a first logical block of data of the first SQE at a first WB, and to provide the first logical block of data to the first allocated WB to provide to the MMS before receiving and providing all of the multiple logical blocks of data of the first SQE to the allocated first plurality of WBs.

### Claim 2 (depends on 1)

The system of claim 1, wherein the VF submission queue circuit is configured determine if there are sufficient resources to hold the one or more received SQEs in the SQ,
wherein, if there are sufficient resources to hold the one or more received SQEs in the SQ, the VF submission queue circuit is configured add the one or more received SQEs to the SQ, and
wherein, if there are insufficient resources to hold the one or more received SQEs in the SQ, the command queue manager circuit is configured to provide a command failure notification.

### Claim 3 (depends on 1)

The system of claim 1, wherein each SQE requires a certain number of allocated WBs to provide write data to the MMS, and
wherein the allocated WBs are free to receive additional write data after write data is provided to the MMS.

### Claim 4 (depends on 1)

The system of claim 1, comprising the first allocated WB configured to receive the first logical block of data and to provide the first logical block of data to the MMS before the host interface circuit receives and provides all logical blocks of data associated with the first SQE to the allocated first plurality of WBs.

### Claim 5 (depends on 1)

The system of claim 1, including:
a non-volatile memory (NVM) controller, including:
the host interface circuit;
a communication interface; and
the MMS,
wherein the MMS is configured to be coupled to a NVM media device,
wherein the host interface circuit is configured to control communication between a client device and the set of VFs using the communication interface, and
wherein the communication interface includes a peripheral component interconnect express (PCIe) interface.

### Claim 6 (depends on 1)

The system of claim 1, wherein the VF submission queue circuit is configured to receive the one or more SQEs and to receive write data using one or more base address registers (BARs) of a communication interface.

### Claim 7 (depends on 1)

The system of claim 1, wherein the command queue manager circuit is configured to receive a read command from the respective VF, to send the read command to the MMS, to receive read data from the MMS corresponding to the read command, and to provide read data to the respective VF.

### Claim 8

A method to control communication between a set of virtual functions (VB) and a media management system (MMS), the method comprising:
consolidating commands from the set of VFs and dynamically allocating write buffers (WBs) from a set of available WBs to the set of VFs using the commands using a command queue manager circuit;
for each VF in the set of VFs:
managing a submission queue (SQ) for a respective VF from the set of VFs, and receiving a command from the respective VF, including one or more submission queue entries (SQEs), using a VF submission queue circuit; and
managing a list of pending writes for the respective VF and coordinating the one or more received SQEs with allocated WBs using a VF write buffer list (WBL) circuit;
managing WB access for the set of VFs and providing write data to the MMS using a WB access circuit;
allocating a first plurality of WBs to receive multiple logical blocks of data of a first SQE;
receiving a first logical block of data of the first SQE at a first WB and providing the first logical block of data to the first allocated WB; and
providing, using the first allocated WB, the first logical block of data to the MMS before all of the multiple logical blocks of data of the first SQE are received and provided to the allocated first plurality of WBs.

### Claim 9 (depends on 8)

The method of claim 8, including:
determining if there are sufficient resources to hold die one or more received SQEs in the SQ; and
if there are sufficient resources to hold the one or more received SQEs in the SQ, adding the one or more received SQEs to the SQ using the VF submission queue circuit; or
if there are insufficient resources to hold the one or more received SQEs in the SQ, providing a command failure notification using the command queue manager circuit.

### Claim 10 (depends on 8)

The method of claim 8, wherein managing WB access for the set of VFs includes:
receiving write data corresponding to an SQE at an allocated WB; and
providing write data from the allocated WB to the MMS,
wherein each SQE requires a certain number of allocated WBs to provide write data to the MMS, and
wherein the allocated WBs from the set of WBs are free to receive additional write data after write data is provided to the MMS.

### Claim 11 (depends on 8)

The method of claim 8, including:
controlling communication between a client device and the set of VFs using a peripheral component interconnect express (PCIe) interface,
wherein providing write data to the MMS includes providing write data to a non-volatile memory (NVM) device.

### Claim 12 (depends on 8)

The method of claim 8, wherein receiving the one or more SQEs and managing WB access for the set of VFs includes using one or more base address registers (BARS) of a communication interface.

### Claim 13

At least one non-transitory machine-readable medium including instructions that, when executed by processing circuitry of a host interface circuit, cause the host interface circuit to control communication between a set of virtual functions (VFs) and a media management system (MMS), including to:
consolidate commands from the set of VFs;
dynamically allocate write buffers (WBs) from a set of available WBs to the set of \Ts using the commands;
for each VF in the set of VFs;
manage a submission queue (SQ) for a respective VF from the set of VFs;
receive a command from the respective VF, including one or more submission queue entries (SQEs); and
coordinate the one or more received SQEs with allocated WBs; and
manage WB access for the set of VFs and provide write data to the MMS using the allocated WBs
allocate a first plurality of WBs to receive multiple logical blocks of data of a first SQE;
receive a first logical block of data of the first SQE at a first WB and provide the first logical block of data to the first allocated WB; and
provide, using the first allocated WB, the first logical block of data to the MMS before all of the multiple logical blocks of data of the first SQE are received and provided to the allocated first plurality of WBs.

### Claim 14 (depends on 13)

The at least one machine-readable medium of claim 13, including instructions that, when executed by the processing circuitry of the host interface circuit, cause the host interface circuit to:
determine if there are sufficient resources to hold the one or more received SQEs in the SQ; and
if there are sufficient resources to hold the one or received SQEs in the SQ, add the one or more received SQEs to the SQ; or
if there are insufficient resources to hold the one or more received SQEs in the SQ, provide a command failure notification.

### Claim 15 (depends on 13)

The at least one machine-readable medium of claim 13, wherein the instructions that, when executed by the processing circuitry of the host interface circuit, cause the host interface circuit to manage WB access for the one or more Ws to the available WBs include instructions to:
receive write data corresponding to an SQE at an allocated WB; and
provide write data from the allocated WB to the MMS,
wherein each SQE requires a certain number of allocated WBs to provide write data to the MMS, and
wherein the allocated Bs from the set of WBs are free to receive additional write data after write data is provided to the MMS.

### Claim 16 (depends on 13)

The at least one machine-readable medium of claim 13, including instructions that, when executed by the processing circuitry of the host interface circuit, cause the host interface circuit to:
control communication between a client device and the set of VFs using a peripheral component interconnect express (PCIe) interface.

### Claim 17 (depends on 13)

The at least one machine-readable medium claim 13, wherein the instructions that, when executed by the processing circuitry of the host interface circuit, cause the host interface circuit to:
receive the one or more SQEs and receive write data from one or more base address registers (BARs) of a communication interface.

### Claim 18 (depends on 13)

The at least one machine-readable medium of claim 13, including instructions that, when executed by the processing circuitry of the host interface circuit, cause the host interface circuit to:
receive a read command from the respective VF;
send the read command to the MMS;
receive read data from the MMS corresponding to the read command; and
provide read data to the respective VF.