# US 10,503,431 B2 · Trade-off adjustments of memory parameters based on memory wear or data retention

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- Number: US 10,503,431 B2
- Document ID: US10503431B2
- Status: Granted
- Kind: B2
- Application number: 14/977,237
- Filed: 2015-12-21
- Published: 2016-06-23
- Granted: 2019-12-10
- Earliest claimed: 2014-12-22
- Assignees: SanDisk Technologies LLC
- Applicants: SanDisk Technologies Inc.
- Inventors: Sergey Anatolievich Gorobets; Neil Richard Darragh; Liam Michael Parker
- Web page: https://patentgrep.com/patent/US10503431B2

## CPC

- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 3/0625: {Power saving in storage systems}
- G06F 3/0634: {by changing the state or mode of one or more devices}
- G06F 11/008: {Reliability or availability analysis}
- G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)}
- G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit}
- G06F 11/079: {Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36)}
- G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/12: Programming voltage switching circuits
- G11C 16/28: using differential sensing or reference cells, e.g. dummy cells
- G11C 16/32: Timing circuits
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 16/3422: {Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem}
- G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles}
- G11C 16/3495: {Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/50004: {of threshold voltage}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 29/70: {Masking faults in memories by using spares or by reconfiguring}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 29/56008: {Error analysis, representation of errors}
- G11C 2029/5004: {Voltage}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.

## Claims

### Claim 1

A method test comprising:
performing, in a storage module, the following:
periodically determining, by generating a histogram, a location of a cell voltage distribution of cells in blocks for at least a portion of the storage module, wherein:
the location corresponds to the location of the cell voltage distribution within the histogram, and
the histogram is generated periodically and corresponds to a distribution of cell voltage states;
measuring changes in the location of the cell voltage distribution from the periodic determinations;
calculating a data retention for the blocks in the at least a portion of the storage module based on the measured changes of the location of the cell voltage distribution; and
dynamically adjusting trim parameters of a block of cells based on the data retention.

### Claim 2 (depends on 1)

The method of claim 1 wherein the trim parameters comprise at least one parameter related to write operations, including a program rate, a program voltage level, a step-up voltage or step size, or a program pulse width.

### Claim 3 (depends on 2)

The method of claim 2 wherein the trim parameters comprise trim settings which further comprise at least one of a sensing time, a sense amplifier delay, or a sense reference voltage.

### Claim 4 (depends on 1)

The method of claim 1 wherein the dynamic adjusting comprises individual adjustments for each block.

### Claim 5 (depends on 4)

The method of claim 4 wherein the dynamic adjusting is performed during run time.

### Claim 6 (depends on 1)

The method of claim 1 wherein the dynamic adjusting further comprises:
adjusting the trim parameters to improve performance with reduced endurance.

### Claim 7 (depends on 6)

The method of claim 6 wherein the adjusting to improve performance is for the blocks with a calculated data retention that is high relative to an initial value of data retention.

### Claim 8 (depends on 1)

The method of claim 1 wherein the dynamic adjusting further comprises:
adjusting the trim parameters to improve endurance with reduced performance.

### Claim 9 (depends on 8)

The method of claim 8 wherein the adjusting to improve endurance is for the blocks with a calculated data retention that is low relative to an initial value of data retention.

### Claim 10 (depends on 1)

The method of claim 1 further comprising:
utilizing a host interface that receives instructions from the host for the adjusting of the trim parameters.

### Claim 11

A method comprising:
performing, with a controller on a memory system, the following:
periodically calculating, a wear for each block in at least a portion of the memory system, by:
measuring a distribution of voltage states for cells in the blocks;
measuring a change in shape of the distribution over a number of measurements; and
quantizing the wear based on changes to the shape of the distribution; and
dynamically adjusting trim parameters for each individual block independent-of other blocks based on the calculated wear for each of those individual blocks.

### Claim 12 (depends on 11)

The method of claim 11 wherein the trim parameters comprise at least one parameter related to read operations, including sensing time, a sense amplifier delay, or a sense reference voltage.

### Claim 13 (depends on 11)

The method of claim 11 wherein the dynamic adjusting comprises individual adjustments for each block that are performed during run time.

### Claim 14 (depends on 11)

The method of claim 11 wherein the dynamic adjusting further comprises:
adjusting the trim parameters to improve performance with reduced endurance.

### Claim 15 (depends on 14)

The method of claim 14 wherein the adjusting to improve performance is for the blocks with a calculated wear that is low.

### Claim 16 (depends on 11)

The method of claim 11 wherein the dynamic adjusting further comprises:
adjusting the trim parameters to improve endurance with reduced performance.

### Claim 17 (depends on 16)

The method of claim 16 wherein the adjusting to improve endurance is for the blocks with a calculated wear that is high.

### Claim 18 (depends on 11)

The method of claim 11 wherein measuring a change in shape comprises at least one selected from the group consisting of: measuring a width of the distribution and measuring a skewness of the distribution.

### Claim 19 (depends on 11)

The method of claim 11 further comprising:
utilizing a host interface with the calculated wear that receives instructions from the host for the adjusting.

### Claim 20

A storage device comprising a controller and memory blocks, wherein the controller is configured for:
periodically determining, by generating a histogram, a cell voltage distribution of cells in the memory device during run time, wherein the histogram is generated periodically;
measuring a change in shape and a change in location of the cell voltage distribution from the periodic determinations, wherein the shape corresponds to a shape of the cell voltage distribution, and the location corresponds to the location of the cell voltage distribution within the histogram;
calculating a wear of the cells based on the shape change from the measured changes in the cell voltage distribution;
calculating a data retention value of the cell based on the location change in the cell voltage distribution; and
dynamically adjusting trim parameters of a block of cells based on the calculated data retention or the calculated wear.