# US 10,503,421 B2 · Configurable memory storage system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,421 B2 - Document ID: US10503421B2 - Status: Granted - Kind: B2 - Application number: 15/938,502 - Filed: 2018-03-28 - Published: 2019-01-03 - Granted: 2019-12-10 - Earliest claimed: 2017-06-30 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Yu-Hao Hsu; Cheng Hung Lee; Chen-Lin Yang; Chiting Cheng; Fu-An Wu; Hung-Jen Liao; Jung-Ping Yang; Jonathan Tsung-Yung Chang; Wei Min Chan; Yen-Huei Chen; Yangsyu Lin; Chien-Chen Lin - Web page: https://patentgrep.com/patent/US10503421B2 ## CPC - G06F 3/0625: {Power saving in storage systems} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 16/12: Programming voltage switching circuits - G11C 16/30: Power supply circuits - H04B 10/03: Arrangements for fault recovery - H04B 10/27: Arrangements for networking - H04J 14/0228: {Wavelength allocation for communications one-to-all, e.g. broadcasting wavelengths} - H04J 14/0268: {Restoration of optical paths, e.g. p-cycles} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - H04B: TRANSMISSION - H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S) ## Abstract Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to control minimize power consumption. ## Claims ### Claim 1 A memory storage system, comprising: biasing circuitry configured to selectively provide a maximum operating voltage signal from among a plurality of operational voltage signals, the plurality of operational voltage signals being a plurality of supply voltages; selection circuitry configured to selectively provide an operating voltage signal from among the plurality of operational voltage signals, the selection circuitry comprising: selection control processing circuitry configured to provide a plurality of switching control signals, wherein at least one switching control signal from among the plurality of switching control signals is at a logical level corresponding to the maximum operating voltage signal, and a plurality of switches configured to selectively provide the operating voltage signal from among the plurality of operational voltage signals in accordance with the plurality of switching control signals; and a memory device configured receive the operating voltage signal. ### Claim 2 (depends on 1) The memory storage system of claim 1, wherein the biasing circuitry is configured to selectively provide the maximum operating voltage signal in accordance with a biasing control signal, the biasing control signal including one or more control bits indicating the maximum operating voltage signal from among the plurality of operational voltage signals. ### Claim 3 (depends on 2) The memory storage system of claim 2, wherein the biasing circuitry comprises: biasing control processing circuitry configured to provide a second plurality of switching control signals in accordance with the biasing control signal; and a second plurality of switches configured to selectively provide the maximum operating voltage signal from among the plurality of operational voltage signals in accordance with the second plurality of switching control signals. ### Claim 4 (depends on 3) The memory storage system of claim 3, wherein at least one switch from among the second plurality of switches comprises: a p-type metal-oxide-semiconductor (PMOS) transistor having a bulk terminal, and further comprising: switch bulk biasing circuitry configured to provide a second maximum operating voltage signal from among the plurality of operational voltage signals to the bulk terminal. ### Claim 5 (depends on 1) The memory storage system of claim 1, wherein the selection circuitry is configured to selectively provide the operating voltage signal in accordance with a selection control signal, the selection control signal including one or more control bits indicating the operating voltage signal from among the plurality of operational voltage signals. ### Claim 6 (depends on 1) The memory storage system of claim 1, wherein each of the plurality of switching control signals activate its corresponding switch from among the plurality of switches when at a first logical level and deactivate its corresponding switch from among the plurality of switches when at a second logical level. ### Claim 7 (depends on 1) The memory storage system of claim 1, wherein at least one switch from among the plurality of switches comprises: a p-type metal-oxide-semiconductor (PMOS) transistor having a bulk terminal, and further comprising: switch bulk biasing circuitry configured to provide a second maximum operating voltage signal from among the plurality of operational voltage signals to the bulk terminal. ### Claim 8 (depends on 1) The memory storage system of claim 1, wherein the selection circuitry is configured to selectively provide the maximum operational voltage signal as the operating voltage signal to maximize a read/write speed of the memory device. ### Claim 9 (depends on 8) The memory storage system of claim 8, wherein the selection circuitry is configured to selectively provide an operational voltage signal less than the maximum operational voltage signal from among the plurality of operational voltage signals as the operating voltage signal to decrease the read/write speed of the memory device. ### Claim 10 (depends on 1) The memory storage system of claim 1, wherein the selection circuitry is configured to selectively provide a minimum operational voltage signal from among the plurality of operational voltage signals as the operating voltage signal to minimize a power consumption of the memory device. ### Claim 11 Selection circuitry for selectively providing an operating voltage signal from among a plurality of operational voltage signals, the selection circuitry comprising: selection control processing circuitry configured to provide a plurality of switching control signals in accordance with a selection control signal, the plurality of operational voltage signals being a plurality of supply voltages, wherein the plurality of switching control signals is referenced to a first domain corresponding to a first operational voltage signal from among the plurality of operational voltage signals, and wherein the selection control signal is referenced to a second domain corresponding to a second operational voltage signal from among the plurality of operational voltage signals, the second operational voltage signal being less than the first operational voltage signal; and a plurality of switches configured to selectively provide the operating voltage signal from among the plurality of operational voltage signals in accordance with the plurality of switching control signals. ### Claim 12 (depends on 11) The selection circuitry of claim 11, wherein at least one switch from among the plurality of switches comprises: a p-type metal-oxide-semiconductor (PMOS) transistor having a bulk terminal, and further comprising: switch bulk biasing circuitry configured to provide a second maximum operating voltage signal from among the plurality of operational voltage signals to the bulk terminal. ### Claim 13 (depends on 11) The selection circuitry of claim 11, wherein the operating voltage signal comprises: a maximum operational voltage signal from among the plurality of operational voltage signals to maximize a read/write speed of a memory device. ### Claim 14 (depends on 13) The selection circuitry of claim 13, wherein the operating voltage signal comprises: a minimum operational voltage signal from among the plurality of operational voltage signals to minimize a power consumption of a memory device. ### Claim 15 Selection circuitry for selectively providing an operating voltage signal from among a plurality of operational voltage signals, the selection circuitry comprising: level shifting circuitry configured to shift a selection control signal from a first domain corresponding to a first operational voltage signal from among the plurality of operational voltage signals to a second domain corresponding to a second operational voltage signal from among the plurality of operational voltage signals to provide a level shifted selection control signal, the second operational voltage signal being less than the first operational voltage signal; a logical inverter configured to perform a logical inverting operation on the level shifted selection control signal to provide at least one switching control signal from among a plurality of switching control signals, wherein the plurality of switching control signals is referenced to the first domain, and wherein the selection control signal is referenced to the second domain; and a plurality of switches configured to selectively provide the operating voltage signal from among the plurality of operational voltage signals in accordance with the plurality of switching control signals. ### Claim 16 A method for operating a memory storage device, the method comprising: receiving, by the memory storage device, a first control signal indicative of a maximum operational voltage signal from among a plurality of operational voltage signals and a second control signal indicative of an operational voltage signal from among the plurality of operational voltage signals, the plurality of operational voltage signals being a plurality of supply voltages; providing, by the memory storage device, the maximum operational voltage signal from among the plurality of operational voltage signals in accordance with the first control signal; shifting, by the memory storage device, the second control signal from a first domain corresponding to an operating voltage signal less than the maximum operational voltage signal from among the plurality of operational voltage signals to a second domain corresponding to the maximum operational voltage signal to provide a plurality of switching control signals in accordance with the second control signal; activating, by the memory storage device, a first switch from among a plurality of switches to selectively provide a first operational voltage signal from among the plurality of operational voltage signals based on a first switching control signal from among the plurality of switching control signals; deactivating, by the memory storage device, a second switch from among the plurality of switches to selectively prohibit the second switch from providing a second operational voltage signal from among the plurality of operational voltage signals based on a second switching control signal from among the plurality of switching control signals; and receiving, by a memory device of the memory storage device, the first operational voltage signal. ### Claim 17 (depends on 16) The method of claim 16, wherein the activating comprises: activating the first switch to selectively provide the maximum operational voltage signal from among the plurality of operational voltage signals based on the first switching control signal from among the plurality of switching control signals. ### Claim 18 (depends on 17) The method of claim 17, wherein the activating further comprises: activating the first switch to selectively provide the maximum operational voltage signal from among the plurality of operational voltage signals based on the first switching control signal from among the plurality of switching control signals to maximize a read/write speed of the memory device. ### Claim 19 (depends on 16) The method of claim 16, wherein the activating comprises: activating the first switch to selectively provide a minimum operational voltage signal from among the plurality of operational voltage signals based on the first switching control signal from among the plurality of switching control signals. ### Claim 20 (depends on 19) The method of claim 19, wherein the activating further comprises: activating the first switch to selectively provide the minimum operational voltage signal from among the plurality of operational voltage signals based on the first switching control signal from among the plurality of switching control signals to minimize a power consumption of the memory device.