# US 10,503,416 B1 · Flash memory complex with a replication interface to replicate data to another flash memory complex of a data processing system

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- Number: US 10,503,416 B1
- Document ID: US10503416B1
- Status: Granted
- Kind: B1
- Application number: 15/629,276
- Filed: 2017-06-21
- Granted: 2019-12-10
- Earliest claimed: 2015-06-10
- Assignees: EMC IP Holdings Company LLC
- Applicants: Emc IP Holding Company LLC
- Inventors: Mark Himelstein; Bruce Wilford; Richard Van Gaasbeck; Todd Wilde; Rick Carlson; Vikram Venkataraghavan; Vishwas Durai; Blair Barnett; Kevin Rowett
- Web page: https://patentgrep.com/patent/US10503416B1

## CPC

- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0635: {by changing the path, e.g. traffic rerouting, path reconfiguration}
- G06F 3/065: {Replication mechanisms}
- G06F 3/067: {Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F 2213/0026: PCI express
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

According to one embodiment, a data processing system includes a plurality of central processing unit (CPU) subsystems, each CPU subsystem having a plurality of CPUs and a plurality of memory controllers, each memory controller corresponding to one of the CPUs, a plurality of memory complexes, each memory complex being associated with one of the CPU subsystems, wherein each memory complex comprises one or more branches, a plurality of memory leaves to store data, wherein each of the branches is coupled to one or more of the memory leaves and to provide access to the data stored in the memory leaves, and a replication interface to automatically replicate data received from one of the CPU subsystems to another one of the memory complexes, wherein the received data is to be stored in one of the memory leaves.

## Claims

### Claim 1

A data processing system, comprising:
a plurality of central processing unit (CPU) subsystems, wherein each CPU subsystem includes a plurality of CPUs and a plurality of memory controllers, each memory controller corresponding to one of the CPUs; and
a plurality of memory complexes, each memory complex being associated with one of the CPU subsystems, wherein each memory complex comprises
a plurality of branches;
a plurality of memory leaves to store data, wherein each of the branches is coupled to one or more of the memory leaves and to provide access to the data stored in the memory leaves, and
a replication interface to automatically replicate data received from one of the CPU subsystems to another one of the memory complexes, wherein the received data is to be stored in one of the memory leaves; and
an Ethernet switch fabric coupled to each of the memory controllers of the CPU subsystems and each of the branches of the memory complexes, wherein each branch of each memory complex that is associated with one of the CPU subsystems is connected to another branch of another memory complex that is associated with another CPU subsystem and can communicate with each other through the Ethernet switch fabric, and the data is replicated via the Ethernet switch fabric,
wherein each of the branches provides access to data stored in local memory leaves by a remote CPU via a remote branch of the remote CPU over the Ethernet switch fabric, without having to invoke a local CPU.

### Claim 2 (depends on 1)

The system of claim 1, further comprising a plurality of dynamic random access memory (DRAM) devices, each DRAM device being coupled to one of the memory controllers via a corresponding memory bus interface.

### Claim 3 (depends on 1)

The system of claim 1, wherein each of the memory leaves comprises one or more solid state memory devices.

### Claim 4 (depends on 1)

The system of claim 1, wherein each of the CPUs of each of the CPU subsystems is coupled to any one of the CPUs of the CPU subsystem via a processor interconnect.

### Claim 5 (depends on 4)

The system of claim 4, wherein the processor interconnect comprises a Quick Path Interconnect™ (QPI).

### Claim 6 (depends on 1)

The system of claim 1, wherein each of the branches provides access to the data stored in the local memory leaves by the local processing unit via a corresponding memory controller.

### Claim 7 (depends on 1)

The system of claim 1, wherein each CPU subsystem is coupled to its associated memory complex via a peripheral component interface express (PCIe) link.

### Claim 8 (depends on 1)

The system of claim 1, wherein each CPU comprises a plurality of CPU cores.

### Claim 9 (depends on 8)

The system of claim 8, wherein each of the processor cores represents a thread processor, and wherein each thread processor is to execute a specific thread.

### Claim 10 (depends on 1)

The system of claim 1, wherein the CPU subsystems are disposed within a processor subsystem chassis of an electronic rack, and wherein each CPU subsystem is disposed on a processor subsystem blade inserted into one of a plurality of slots within the processor subsystem chassis.

### Claim 11 (depends on 10)

The system of claim 10, wherein the memory complexes are disposed within a memory subsystem chassis of the electronic rack, and wherein each memory complex is disposed on a memory subsystem blade inserted into one of a plurality of slots within the memory subsystem chassis.