# US 10,503,414 B2 · Memory system and method for operating the memory system

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- Number: US 10,503,414 B2
- Document ID: US10503414B2
- Status: Granted
- Kind: B2
- Application number: 15/408,911
- Filed: 2017-01-18
- Published: 2018-03-01
- Granted: 2019-12-10
- Earliest claimed: 2016-08-25
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Won-Jin Jung
- Web page: https://patentgrep.com/patent/US10503414B2

## CPC

- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/064: {Management of blocks}
- G06F 3/065: {Replication mechanisms}
- G06F 3/0665: {at area level, e.g. provisioning of virtual or logical volumes}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 3/0689: {Disk arrays, e.g. RAID, JBOD}
- G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits}
- G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/10: Programming or data input circuits
- G11C 29/24: Accessing extra cells, e.g. dummy cells or redundant cells
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 29/70: {Masking faults in memories by using spares or by reconfiguring}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G06F 2212/7207: management of metadata or control data
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G11C 2211/5646: Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory system may include: a memory device including a memory cell array, the memory cell array including a plurality of scan areas, each of the plurality of the scan areas including at least two group areas, each of the group areas including a flag area storing a flag that represents whether a corresponding group area is programmed or not; and a controller suitable for requesting the memory device to read the flag of each of the group areas a flag when a sudden power-off occurs, and rebuilding at least one of the group areas when at least one of the flags is in an erase state.

## Claims

### Claim 1

A memory system, comprising:
a memory device including a memory cell array, the memory cell array including a plurality of scan areas, each of the plurality of the scan areas including at least two group areas, each including plural pages and a single flag area storing a flag that represents whether the plural pages of each of the group areas are programmed or not, wherein the flag is set when a program operation onto the plural pages of each of the group areas is completed; and
a controller suitable for requesting the memory device to read the flag of each of the group areas after a sudden power-off occurs, searching which flag is in an erase state, and starting a rebuilding operation from at least one of the group areas, which includes an erase-state flag,
wherein the controller scans only the group area at which the program operation stopped among the plurality of scan areas so as to reduce the time taken for a rebuild operation.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the plurality of the scan areas of the memory cell array are blocks, and each of the blocks includes the group areas.

### Claim 3 (depends on 2)

The memory system of claim 2, wherein the single flag area of each of the group areas is disposed in a last word line of the group.

### Claim 4 (depends on 2)

The memory system of claim 2, wherein when a program operation performed onto a scan area is completed for one of the group areas, the memory device programs the flag for the group for which the program operation is completed.

### Claim 5 (depends on 4)

The memory system of claim 4, wherein after a sudden power-off, the controller searches for an open block included in the memory device, obtains address information of the searched open block, and transfers a flag read command and the address information of the searched open block to the memory device.

### Claim 6 (depends on 5)

The memory system of claim 5, wherein the memory device receives the flag read command, reads flags of groups corresponding to the address information of the searched open block, and transfers flag information regarding the flags to the controller.

### Claim 7 (depends on 6)

The memory system of claim 6, wherein the controller transfers address information of a group corresponding to a first erase-state flag among the received flag information and a read command to the memory device, and determines the data received from the memory device and rebuilds a program area of the group whose programming stopped due to the sudden power-off.

### Claim 8 (depends on 7)

The memory system of claim 7, wherein the controller controls the memory device to program data continuously from a position that is lastly programmed in the open block.

### Claim 9 (depends on 3)

The memory system of claim 3, wherein the memory device further includes a sudden power-off sensing circuit, and
when a sudden power-off sensing command is received from the controller, the memory device transfers a sensing data by the sudden power-off sensing circuit to the controller.

### Claim 10 (depends on 9)

The memory system of claim 9, wherein the sudden power-off sensing circuit determines occurrence of a sudden power-off based on a sequence and temporal term between a word line signal and a bit line signal being shut off.

### Claim 11

A method for operating a memory system, comprising:
determining occurrence of a sudden power-off in a memory device that includes a memory cell array including a plurality of scan areas, each of the plurality of the scan areas including at least two group areas, each including plural pages and a single flag area for storing a flag that represents whether the plural pages of each of the group areas are programmed or not, wherein the flag is set when a program operation onto the plural pages of each of the group areas is completed;
receiving flags for the group areas from the memory device when a power supply is resumed after the sudden power-off;
searching which flag is in an erase state; and
starting a rebuilding operation from at least one of the group areas, which includes an erase-state flag,
wherein the starting the rebuilding operation includes scanning only the group area at which the program operation stopped among the plurality of scan areas so as to reduce the time taken for a rebuild operation.

### Claim 12 (depends on 11)

The method of claim 11, wherein the plurality of the scan areas of the memory cell array are blocks, and each of the blocks includes the group areas.

### Claim 13 (depends on 12)

The method of claim 12, wherein the single flag area of each of the group areas is disposed in a last word line of the group.

### Claim 14 (depends on 12)

The method of claim 12, further comprising:
when a program operation performed onto a scan area is completed for one of the group areas, programming the flag for the group for which the program operation is completed.

### Claim 15 (depends on 14)

The method of claim 14, wherein the receiving of the flags for the group areas from the memory device when the power supply is resumed after the sudden power-off includes:
searching for an open block included in the memory device where the program operation stopped, when the power supply is resumed after the sudden power-off; and
reading the flags of the searched open block.

### Claim 16 (depends on 15)

The method of claim 15, wherein the rebuilding of the group corresponding to the erase-state flag among the read flags includes:
determining whether the flags are in a program state or an erase state;
determining a program state of the group corresponding to a first erase-state flag among the flags; and
rebuilding the group corresponding to the first erase-state flag.

### Claim 17 (depends on 16)

The method of claim 16, wherein the determining of the program state of the group corresponding to the erase-state flag among the read flags further includes:
not scanning groups corresponding to programmed flags among the received flags.

### Claim 18 (depends on 16)

The method of claim 16, further comprising:
programming data continuously from a position that is programmed lastly in the open block, after the rebuilding of the group corresponding to the erase-state flag among the read flags.

### Claim 19 (depends on 13)

The method of claim 13, further comprising:
determining the occurrence of the sudden power-off through the memory device including the sudden power-off sensing circuit,
wherein the determining of the occurrence of the sudden power-off through the memory device including the sudden power-off sensing circuit includes:
requesting to transfer a sudden power-off sensing command to the memory device; and
determining the occurrence of the sudden power-off by reading a sudden power-off sensing data that is received from the memory device.

### Claim 20 (depends on 13)

The method of claim 13, further comprising:
determining the occurrence of the sudden power-off in a host device, wherein the memory system is a Solid-State Drive (SSD).