# US 10,503,410 B2 · Apparatus and method for enforcing timing requirements for a memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,410 B2 - Document ID: US10503410B2 - Status: Granted - Kind: B2 - Application number: 16/116,813 - Filed: 2018-08-29 - Published: 2019-01-10 - Granted: 2019-12-10 - Earliest claimed: 2015-12-16 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Jason K. Yu - Web page: https://patentgrep.com/patent/US10503410B2 ## CPC - G06F 3/0611: {in relation to response time} - G06F 3/0653: {Monitoring storage devices or systems} - G06F 3/0688: {Non-volatile semiconductor memory arrays} - G06F 12/0866: for peripheral storage systems, e.g. disk cache - G06F 12/0877: Cache access modes - G06F 2212/1024: Latency reduction - G06F 2212/60: Details of cache memory - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Provided are an apparatus and method for enforcing timing requirements for a memory device. An event command directed to a target addressable location comprising one of the addressable locations is received. A determination is made as to whether a time difference of a current time and a timestamp associated with a completed event directed to a threshold location including the target addressable location exceeds a time threshold. The received event command is executed against the target addressable location in response to determining that the time difference exceeds the time threshold. ## Claims ### Claim 1 An apparatus comprising: an interface to connect with one or more memory devices based at least, in part, on a connection of the one or more memory devices with the interface and a controller, coupled to the interface, the controller to: receive a command A associated with a region of a memory device; store a time stamp associated with the command A; receive a command B associated with at least a portion of the region of the memory device; determine a time stamp associated with the command B; determine a time difference between the time stamp associated with the command B and the time stamp associated with the command A, wherein the command A comprises a last completed command for the region of the memory device; permit execution of the command B to proceed in response to the time difference meeting or exceeding a time gap; and allow execution of the command B in response to a difference between a current time and the time stamp associated with the command A meets or exceeds the time gap. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the time stamp associated with the command A comprises a completion or processing of the command A and the time stamp associated with the command B comprises a receipt of the command B. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the time gap is based at least, in part, on a type of command A and a type of command B, the type of command A comprises read or write, and the type of command B comprises read or write. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the time gap is based at least, in part, on a type of command A and a type of command B, in response to the type of command A comprising a read and the type of command B comprising a read, the time gap is time W, in response to the type of command A comprising a read and the type of command B comprising a write, the time gap is time X, in response to the type of command A comprising a write and the type of command B comprising a read, the time gap is time Y, in response to the type of command A comprising a write and the type of command B comprising a write, the time gap is time Z, and W, X, Y, and Z are the same or different values. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the region is based at least, in part, on one or more addresses associated with one or more of: a die or partition. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein to determine a time gap being met or exceeded, the controller is to: associate a flag with the region; set the flag to indicate a not ready state in response to the time gap not being met or exceeded based on a difference between a current time and the time stamp associated with the command A; and set the flag to indicate a ready state in response to the time gap being met or exceeded based on a difference between the current time and the time stamp associated with the command A, wherein the ready state is to indicate that a received command directed to at least a portion of the region of the memory device is to commence execution. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein: the controller is to store a time stamp associated with processing or completion of command B and the stored time stamp associated with processing or completion of command B is to be used to determine when another received command directed to at least a portion of the region of the memory device is to commence execution. ### Claim 8 (depends on 1) The apparatus of claim 1, further comprising the one or more memory devices coupled to the interface, wherein the one or more memory devices comprise one or more of: a non-volatile memory and a dynamic random access memory (DRAM) and wherein the non-volatile memory comprises one or more of: three dimensional multilayer stacked crosspoint memory array, NAND memory cells, ferroelectric random-access memory (FeTRAM), nanowire-based non-volatile memory, phase change memory (PCM), memristor, magnetoresistive random-access memory (MRAM), Spin Transfer Torque (STT)-MRAM, or Resistive Random Access Memory (ReRAM). ### Claim 9 A method comprising: receiving a command A associated with a region of a memory device; storing a time stamp associated with the command A; receiving a command B associated with at least a portion of the region of the memory device; determining a time stamp associated with the command B; determining a time difference between the time stamp associated with the command B and the time stamp associated with the command A, wherein the command A comprises a last completed command for the region of the memory device; permitting execution of the command B to proceed in response to the time difference meeting or exceeding a time gap; and permitting execution of the command B in response to a difference between a current time and the time stamp associated with the command A meeting or exceeding the time gap. ### Claim 10 (depends on 9) The method of claim 9, wherein the time stamp associated with the command A comprises a completion or processing of the command A and the time stamp associated with the command B comprises a receipt of the command B. ### Claim 11 (depends on 9) The method of claim 9, wherein the time gap is based at least, in part, on a type of command A and a type of command B, in response to the type of command A comprising a read and the type of command B comprising a read, the time gap is time W, in response to the type of command A comprising a read and the type of command B comprising a write, the time gap is time X, in response to the type of command A comprising a write and the type of command B comprising a read, the time gap is time Y, in response to the type of command A comprising a write and the type of command B comprising a write, the time gap is time Z, and W, X, Y, and Z are the same or different values. ### Claim 12 (depends on 9) The method of claim 9, wherein the region is based at least, in part, on one or more addresses associated with one or more of: a die or partition and the memory device comprises one or more of: a non-volatile memory and a dynamic random access memory (DRAM) and wherein the non-volatile memory comprises one or more of: three dimensional multilayer stacked crosspoint memory array, NAND memory cells, ferroelectric random-access memory (FeTRAM), nanowire-based non-volatile memory, phase change memory (PCM), memristor, magnetoresistive random-access memory (MRAM), Spin Transfer Torque (STT)-MRAM, or Resistive Random Access Memory (ReRAM). ### Claim 13 An apparatus comprising: a controller means comprising: means for receiving a command A associated with a region of a memory device; means for storing a time stamp associated with the command A; means for receiving a command B associated with at least a portion of the region of the memory device; means for determining a time stamp associated with the command B; means for determining a time difference between the time stamp associated with the command B and the time stamp associated with the command A, wherein the command A comprises a last completed command for the region of the memory device; means for permitting execution of the command B to proceed in response to the time difference meeting or exceeding a time gap; and means for permitting execution of the command B in response to a time difference between a current time stamp and the time stamp associated with the command A meeting or exceeding the time gap. ### Claim 14 A system comprising: one or more processors; one or more memory devices; and a controller, coupled to the one or more processors and the one or more memory devices, the controller to: receive a command A associated with a region of a memory device; store a time stamp associated with the command A; receive a command B associated with at least a portion of the region of the memory device; determine a time stamp associated with the command B; determine a time difference between the time stamp associated with the command B and the time stamp associated with the command A, wherein the command A comprises a last completed command for the region of the memory device; permit execution of the command B to proceed in response to the time difference meeting or exceeding a time gap; and permit execution of the command B in response to a difference between a current time and the time stamp associated with the command A meets or exceeds the time gap. ### Claim 15 (depends on 14) The system of claim 14, wherein the time stamp associated with the command A comprises a completion or processing of the command A and the time stamp associated with the command B comprises a receipt of the command B. ### Claim 16 (depends on 14) The system of claim 14, wherein the time gap is based at least, in part, on a type of command A and a type of command B, the type of command A comprises read or write, and the type of command B comprises read or write. ### Claim 17 (depends on 14) The system of claim 14, wherein the time gap is based at least, in part, on a type of command A and a type of command B, in response to the type of command A comprising a read and the type of command B comprising a read, the time gap is time W, in response to the type of command A comprising a read and the type of command B comprising a write, the time gap is time X, in response to the type of command A comprising a write and the type of command B comprising a read, the time gap is time Y, in response to the type of command A comprising a write and the type of command B comprising a write, the time gap is time Z, and W, X, Y, and Z are the same or different values. ### Claim 18 (depends on 14) The system of claim 14, wherein the region is based at least, in part, on one or more addresses associated with one or more of: a die or partition. ### Claim 19 (depends on 14) The system of claim 14, wherein: the controller is to store a time stamp associated with processing or completion of command B and the stored time stamp associated with processing or completion of command B is to be used to determine when another received command directed to at least a portion of the region of the memory device is to commence execution. ### Claim 20 (depends on 14) The system of claim 14, wherein the one or more memory devices comprise one or more of: a non-volatile memory and a dynamic random access memory (DRAM) and wherein the non-volatile memory comprises one or more of: three dimensional multilayer stacked crosspoint memory array, NAND memory cells, ferroelectric random-access memory (FeTRAM), nanowire-based non-volatile memory, phase change memory (PCM), memristor, magnetoresistive random-access memory (MRAM), Spin Transfer Torque (STT)-MRAM, or Resistive Random Access Memory (ReRAM).