# US 10,503,407 B2 · Memory system and method for controlling nonvolatile memory

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- Number: US 10,503,407 B2
- Document ID: US10503407B2
- Status: Granted
- Kind: B2
- Application number: 15/914,009
- Filed: 2018-03-07
- Published: 2019-03-21
- Granted: 2019-12-10
- Earliest claimed: 2017-09-21
- Assignees: Toshiba Memory Corporation
- Applicants: Toshiba Memory Corporation
- Inventors: Hideki Yoshida; Shinichi Kanno
- Web page: https://patentgrep.com/patent/US10503407B2

## CPC

- G06F 3/061: {Improving I/O performance}
- G06F 3/0616: {in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]}
- G06F 3/064: {Management of blocks}
- G06F 3/0658: {Controller construction arrangements}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 12/1009: using page tables, e.g. page table structures
- G06F 2212/1016: Performance improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/1036: Life time enhancement
- G06F 2212/2022: Flash memory
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7205: Cleaning, compaction, garbage collection, erase control
- G06F 2212/7207: management of metadata or control data
- G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.

## Claims

### Claim 1

A memory system connectable to a host, comprising:
a nonvolatile memory including a plurality of blocks each including a plurality of pages; and
a controller electrically connected to the nonvolatile memory to control the nonvolatile memory,
wherein the controller is configured, when receiving a write request to designate a first block number and a first logical address from the host, to determine a first location in a first block having the first block number, to which data from the host is to be written, to write the data from the host to the first location of the first block, to update a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block but not mapping between the logical addresses and a physical address of the first block, and to map a first in-block physical address indicative of the first location to the first logical address, and when receiving a read request to designate the first block number and the first logical address from the host, to acquire the first in-block physical address by referring to the first address translation table using the first logical address, and to read data corresponding to the first logical address from the nonvolatile memory, based on the first block number and the acquired first in-block physical address.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the first in-block physical address is represented by a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of a grain having a size different from a page size.

### Claim 3 (depends on 1)

The memory system of claim 1, wherein the controller is configured, when receiving from the host a control command designating a copy source block number and a copy destination block number for garbage collection of the nonvolatile memory, to select a second block having the copy source block number and a third block having the copy destination block number, of the plurality of blocks, to determine a copy destination location in the third block to which valid data stored in the second block is to be written, and to copy the valid data to the copy destination location of the third block.

### Claim 4 (depends on 3)

The memory system of claim 3, wherein the controller is configured to update a second address translation table managing mapping between logical addresses and in-block physical addresses of the second block, and a third address translation table managing mapping between logical addresses and in-block physical addresses of the third block, such that an in-block physical address mapped to a logical address of the valid data is changed from a second in-block physical address indicative of a copy source location in the second block in which the valid data is stored to a third in-block physical address indicative of the copy destination location of the third block.

### Claim 5 (depends on 4)

The memory system of claim 4, wherein the second in-block physical address is represented by a second in-block offset indicating an offset from a leading part of the second block to the copy source location by a multiple of a grain having a size different from a page size, and the third in-block physical address is represented by a third in-block offset indicating an offset from a leading part of the third block to the copy destination location by a multiple of the grain.

### Claim 6 (depends on 3)

The memory system of claim 3, wherein the controller is configured to notify the host of a logical address of the valid data and the copy destination block number to which the valid data is copied.

### Claim 7 (depends on 1)

The memory system of claim 1, wherein the controller is configured, when receiving a first command to request a maximum block number from the host, to notify the host of the maximum block number indicative of number of the plurality of blocks, and when receiving a second command to request a block size from the host, to notify the host of the block size of each of the plurality of blocks.

### Claim 8 (depends on 7)

The memory system of claim 7, wherein the controller is configured, if a block number is included in the second command, to notify the host of a block size of a block having the block number included in the second command.

### Claim 9 (depends on 7)

The memory system of claim 7, wherein the controller is configured, when receiving from the host a control command designating a plurality of copy source block numbers and a plurality of copy destination block numbers for garbage collection of the nonvolatile memory, to select a plurality of second blocks having the plurality of copy source block numbers and a plurality of third blocks having the plurality of copy destination block numbers, of the plurality of blocks, to determine a copy destination location in one of the plurality of third blocks to which valid data stored in one of the second blocks is to be written, to copy the valid data to the copy destination location of the third block, and to notify the host of the logical address of the copied valid data and the block number of the third block.

### Claim 10

A memory system connectable to a host, comprising:
a nonvolatile memory including a plurality of blocks each including a plurality of pages; and
a controller electrically connected to the nonvolatile memory to control the nonvolatile memory,
wherein the controller is configured, when receiving a first command requesting a maximum block number from the host, to notify the host of the maximum block number indicative of number of the plurality of blocks, when receiving a second command requesting a block size from the host, to notify the host of the block size of each of the plurality of blocks, when receiving a write request to designate a first block number and a first logical address from the host, to determine a first location in a first block having the first block number, to which data from the host is to be written, to write the data from the host to the first location of the first block, to update a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and to map a first in-block physical address indicative of the first location to the first logical address, when receiving a read request to designate the first block number and the first logical address from the host, to acquire the first in-block physical address by referring to the first address translation table using the first logical address, and to read data corresponding to the first logical address from the nonvolatile memory, based on the first block number and the acquired first in-block physical address.

### Claim 11 (depends on 10)

The memory system of claim 10, wherein the first in-block physical address is represented by a first in-block offset indicating an offset from a leading part of the first block to the first location by a multiple of a grain having a size different from a page size.

### Claim 12

A method of controlling a nonvolatile memory including a plurality of blocks each including a plurality of pages, the method comprising:
when receiving a write request to designate a first block number and a first logical address from a host, executing an operation of determining a first location in a first block having the first block number, to which data from the host is to be written, an operation of writing the data from the host to the first location of the first block, an operation of updating a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block but not mapping between the logical addresses and a physical address of the first block, and an operation of mapping a first in-block physical address indicative of the first location to the first logical address; and
when receiving a read request to designate the first block number and the first logical address from the host, executing an operation of acquiring the first in-block physical address by referring to the first address translation table using the first logical address, and an operation of reading data corresponding to the first logical address from the nonvolatile memory, based on the first block number and the acquired first in-block physical address.