# US 10,503,402 B2 · Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,402 B2 - Document ID: US10503402B2 - Status: Granted - Kind: B2 - Application number: 15/855,693 - Filed: 2017-12-27 - Published: 2018-05-17 - Granted: 2019-12-10 - Earliest claimed: 2015-05-15 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Daniel G. Berger; Troy L. Graves-Abe; Subramanian S. Iyer; Toshiaki Kirihata; Arvind Kumar; Winfried W. Wilcke - Web page: https://patentgrep.com/patent/US10503402B2 ## CPC - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0629: {Configuration or reconfiguration of storage systems} - G06F 3/0673: {Single storage device} - H10W 90/00: Package configurations - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 72/01: {Manufacture or treatment} - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer. ## Claims ### Claim 1 A stacked-wafer processor-memory system comprising: a plurality of specialized processor wafers arranged in a stack, each of the specialized processor wafers comprising a memory area and a multitude of specialized processors embedded in the memory area of the each specialized processor wafer, and each of the specialized processors performing a specified set of operations using a respective one associated memory domain of the memory area of the each specialized processor wafer; an input/output connection; a plurality of subordinate general management processors, each of the subordinate general management processors connected to an associated set of the specialized processors; and a lead general management processor in communication with the input/output connection and with the subordinate general management processors for transmitting data to and receiving data from the subordinate general management processors; a plurality of protocol converter chips, wherein each of the subordinate general management processors is connected to one of the protocol converter chips to allow the specialized processors to communicate with the subordinate general management processors. ### Claim 2 (depends on 1) The stacked-wafer processor-memory system according to claim 1, wherein: each of the specialized processor wafers further comprises a wiring level connecting together the specialized processors of the each specialized processor wafer. ### Claim 3 (depends on 1) The stacked-wafer processor-memory system according to claim 1, further comprising: a network of inter-strata through silicon vias for delivering power and ground to the specialized processor wafers. ### Claim 4 (depends on 2) The stacked-wafer processor-memory system according to claim 2, further comprising: a wiring wafer comprising a plurality of wiring levels; and wherein: the lead general management processor and the plurality of subordinate general management processors are connected to the wiring levels of the wiring wafer. ### Claim 5 (depends on 4) The stacked-wafer processor memory system according to claim 4, wherein: the wiring wafer is mounted on top of the plurality of specialized processor wafers. ### Claim 6 (depends on 1) The stacked-wafer integrated circuit according to claim 1, further comprising an interposer, and wherein: the plurality of specialized processor wafers are stacked on the interposer. ### Claim 7 (depends on 6) The stacked-wafer integrated circuit according to claim 6, wherein: the lead general management processor and the subordinate general management processors are mounted on the interposer. ### Claim 8 (depends on 1) The stacked-wafer integrated circuit according to claim 1, wherein: each of the specialized processors is embedded within the associated memory domain of the memory area. ### Claim 9 (depends on 8) The stacked-wafer integrated circuit according to claim 8, wherein: each of the specialized processors controls the associated memory domain of the memory area. ### Claim 10 (depends on 1) The stacked-wafer integrated circuit according to claim 1, wherein: each of the specified processors is embedded within and controls a respective one associated memory domain of the memory area; and the lead general management processor controls the general management processors to implement hierarchical processing in the stacked-wafer integrated circuit. ### Claim 11 A method of fabricating a stacked wafer processor-memory system, the method comprising: fabricating a plurality of specialized processor wafers, each of the specialized processor wafers comprising a memory area and a multitude of specialized processors embedded in the memory area of the each specialized processor wafer, each of the specialized processors being configured to perform a specified set of operations using an associated memory domain of the memory area of the each specialized processor wafer; connecting a plurality of subordinate general management processors to the specialized processors, each of the subordinate general management processors being configured to manage an associated set of the specialized processors; connecting a lead general management processor to an input/output connection and to the subordinate general management processors to communicate therewith; connecting each of the subordinate general management processor to a protocol converter chip to allow the specialized processors to communicate with the subordinate general management processors; and forming a network of inter-strata through silicon vias for delivering power and ground to the specialized processor wafers. ### Claim 12 (depends on 11) The method according to claim 11, further comprising: fabricating a wiring wafer, said wiring waver including wiring levels for the lead general management processor and the subordinate general management processors; and wherein: the connecting a plurality of subordinate general management processors to the specialized processors includes connecting the plurality of subordinate general management processors to the wiring levels of the wiring wafer; and the connecting a lead general management processor to the subordinate general management processors includes connecting the lead general management processor to the wiring levels of the wiring wafer. ### Claim 13 (depends on 12) The method according to claim 12, wherein the connecting the plurality of subordinate general management processors to the wiring levels of the wiring wafer includes bonding the plurality of subordinate general management processors to the wiring wafer using a layer of micro controlled collapse-chip connections. ### Claim 14 (depends on 11) The method according to claim 11, wherein the fabricating a plurality of specialized processor wafers includes adding a wiring level to each of the specialized processor wafers to connect together the specialized processors of the each specialized processor wafer. ### Claim 15 (depends on 11) The method according to claim 11, further comprising: bonding the plurality of specialized processor wafers together into a stack; mounting said stack onto an interposer board; and wherein: the connecting a lead general management processor to the subordinate general management processors includes mounting the lead general management processor on the interposer board; and the connecting a plurality of subordinate general management processors to the specialized processors includes mounting the subordinate general management processors on the interposer board. ### Claim 16 A stacked-wafer processor-memory system comprising: a plurality of wafers arranged in a stack, including at least one memory wafer comprising a multitude of memory domains, and at least one processor wafer comprising a multitude of specialized processors, each of the specialized processors controlling a respective one of the memory domains of the memory wafer; an input/output connection; a multitude of general management processors including a multitude of subordinate general management processors, each of the subordinate general management processors being connected to a respective one, associated set of the specialized processors for controlling said associated set of the specialized processors, and a lead general management processor in communication with the input/output connection and with the subordinate general management processors for transmitting data to and receiving data from the subordinate general management processors; a plurality of protocol converter chips, wherein each of the subordinate general management processors is connected to one of the protocol converter chips to allow the specialized processors to communicate with the subordinate general management processors; and a network of through silicon vias for delivering power and ground to the specialized processor wafers and for communicating with the general management processors. ### Claim 17 (depends on 16) The stacked-wafer processor-memory system according to claim 16, wherein: the at least one memory wafer includes a plurality of memory wafers; the at least one processor wafer includes a plurality of processor wafers; and in said stack, the plurality of memory wafer alternate with the plurality of processor wafers. ### Claim 18 (depends on 17) The stacked-wafer processor-memory system according to claim 17, wherein: each of the plurality of processor wafers includes a wiring level connecting together the processors of said each processor wafer. ### Claim 19 (depends on 16) The cortical structure according to claim 16, further comprising: a wiring wafer; and wherein: the multitude of general management processors are mounted on the wiring wafer. ### Claim 20 (depends on 19) The stacked-wafer processor-memory system according to claim 19, wherein the wiring wafer is mounted on said stack.