# US 10,503,203 B2 · Low-power multi-phase clock distribution on silicon > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,203 B2 - Document ID: US10503203B2 - Status: Granted - Kind: B2 - Application number: 15/838,683 - Filed: 2017-12-12 - Published: 2019-06-13 - Granted: 2019-12-10 - Earliest claimed: 2017-12-12 - Assignees: Advanced Micro Devices, Inc. - Applicants: Dirk J. Robinson - Inventors: Dirk J. Robinson - Web page: https://patentgrep.com/patent/US10503203B2 ## CPC - G06F 1/10: Distribution of clock signals {, e.g. skew} - H03K 19/096: Synchronous circuits, i.e. using clock signals {(H03K19/01728, H03K19/01855 take precedence)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Various semiconductor chip clock signal pathways are disclosed. In one aspect, a semiconductor chip with a receiver includes a clock signals pathway for conveying plural clock phases in the receiver. The clock signals pathway includes plural wires in an arrangement that has a first edge, a second edge separated from the first edge and a midline between the first edge and the second edge. Each of the wires conveys a clock phase. The wires of the arrangement are routed so that, along a length of the clock signals pathway, each of the wires spends about the same percentage of time at or nearer the first edge or the second edge and at or nearer the midline. ## Claims ### Claim 1 A semiconductor chip having a receiver, comprising: a clock signals pathway for conveying plural clock phases in the receiver, the clock signals pathway including plural wires in an arrangement having a first edge, a second edge separated from the first edge and a midline between the first edge and the second edge, each of the wires conveying a clock phase; and the wires of the arrangement being routed so that, along a length of the clock signals pathway, each of the wires spends about the same percentage of time at or nearer the first edge or the second edge and at or nearer the midline. ### Claim 2 (depends on 1) The semiconductor chip of claim 1, wherein the arrangement includes a first crossover to rotate one of the wires from a first position nearer the first edge or the second edge to a second position nearer the midline and rotate another of the wires from a third position nearer the midline to a fourth position nearer the first edge or the second edge, and a second crossover longitudinally separated from the first crossover to rotate the one of the wires from the second position nearer the midline to the first position nearer the first edge or the second edge and rotate the another of the wires from the fourth position nearer the midline to the third position nearer the first edge or the second edge. ### Claim 3 (depends on 2) The semiconductor chip of claim 2, wherein the wires comprise two conductor layers, a first of the conductor layers having the one of the wires and the second of the conductor layers having a first crossover wire connecting the one of the wires to another wire in the first conductor layer. ### Claim 4 (depends on 3) The semiconductor chip of claim 3, wherein the second conductor layer not including a crossover wire connects the another of the wires to another wire in the first conductor layer. ### Claim 5 (depends on 3) The semiconductor chip of claim 3, comprising plural conductive vias connecting the first crossover wire to the first conductor layer. ### Claim 6 (depends on 2) The semiconductor chip of claim 2, wherein the clock phases are in cyclical order going into and out of the first and second crossovers. ### Claim 7 (depends on 1) The semiconductor chip of claim 1, wherein the receiver is configured to receive data signals from a transmitter and configured to use one or a combination of the clock phases to adjust phase of the data signals. ### Claim 8 A semiconductor chip having a receiver, comprising: a clock signals pathway for conveying plural clock phases and plural dummy clock phases in the receiver, the clock signals pathway including plural wires in an arrangement having a first side and a second side, each of the wires conveying a clock phase or a dummy clock phase; a first group of the wires carrying the plural clock phases in order; a second group of the wires carrying the plural dummy clock phases, the second group of wires bracketing the first group of wires; and first and second ground wires bracketing the plural wires. ### Claim 9 (depends on 8) The semiconductor chip of claim 8, wherein one or more of the wires conveying dummy clock phases can be selectively enabled or disabled. ### Claim 10 (depends on 8) The semiconductor chip of claim 8, wherein a last wire in the first group proximate the first side has a first phase, the wires of the second group positioned proximate the last wire in the first group having phase differences relative to the first phase that increase with increasing distance from the last wire of the first group, and wherein a last wire in the first group proximate the second side has a second phase, the wires of the second group positioned proximate the last wire in the first group having phase differences relative to the second phase that increase with increasing distance from the last wire of the first group proximate the second side. ### Claim 11 A method of manufacturing a semiconductor chip having a receiver, comprising: fabricating a clock signals pathway for conveying plural clock phases in the receiver, the clock signals pathway including plural wires in an arrangement having a first edge, a second edge separated from the first edge and a midline between the first edge and the second edge, each of the wires conveying a clock phase; and routing the wires of the arrangement so that, along a length of the clock signals pathway, each of the wires spends about the same percentage of time at or nearer the first edge or the second edge and at or nearer the midline. ### Claim 12 (depends on 11) The method of claim 11, wherein the arrangement includes a first crossover to rotate one of the wires from a first position nearer the first edge or the second edge to a second position nearer the midline and rotate another of the wires from a third position nearer the midline to a fourth position nearer the first edge or the second edge, and a second crossover longitudinally separated from the first crossover to rotate the one of the wires from the second position nearer the midline to the first position nearer the first edge or the second edge and rotate the another of the wires from the fourth position nearer the midline to the third position nearer the first edge or the second edge. ### Claim 13 (depends on 12) The method of claim 12, wherein the wires comprise two conductor layers, a first of the conductor layers having the one of the wires and the second of the conductor layers having a first crossover wire connecting the one of the wires to another wire in the first conductor layer. ### Claim 14 (depends on 13) The method of claim 13, wherein the second conductor layer not including a crossover wire connects the another of the wires to another wire in the first conductor layer. ### Claim 15 (depends on 14) The method of claim 14, comprising fabricating plural conductive vias connecting the first crossover wire to the first conductor layer. ### Claim 16 (depends on 12) The method of claim 12, wherein the clock phases are in cyclical order going into and out of the first and second crossovers. ### Claim 17 (depends on 11) The method of claim 11, wherein the receiver is configured to receive data signals from a transmitter and configured to use one or combined multiple of the clock phases to adjust phase of the data signals. ### Claim 18 A method of manufacturing a semiconductor chip having a receiver, comprising: fabricating a clock signals pathway for conveying plural clock phases and plural dummy clock phases in the receiver, the clock signals pathway including plural wires in an arrangement having a first side and a second side, each of the wires conveying a clock phase or a dummy clock phase; a first group of the wires carrying the plural clock phases in order; a second group of the wires carrying the plural dummy clock phases, the second group of wires bracketing the first group of wires; and fabricating first and second ground wires bracketing the plural wires. ### Claim 19 (depends on 18) The method of claim 18, wherein one or more of the wires conveying dummy clock phases can be selectively enabled or disabled. ### Claim 20 (depends on 18) The method of claim 18, wherein a last wire in the first group proximate the first side has a first phase, the wires of the second group positioned proximate the last wire in the first group having phase differences relative to the first phase that increase with increasing distance from the last wire of the first group, and wherein a last wire in the first group proximate the second side has a second phase, the wires of the second group positioned proximate the last wire in the first group having phase differences relative to the second phase that increase with increasing distance from the last wire of the first group proximate the second side.