# US 10,503,201 B2 · Drift tracking feedback for communication channels

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- Number: US 10,503,201 B2
- Document ID: US10503201B2
- Status: Granted
- Kind: B2
- Application number: 15/616,795
- Filed: 2017-06-07
- Published: 2017-11-30
- Granted: 2019-12-10
- Earliest claimed: 2004-03-17
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Scott C. Best; Abhijit M. Abhyankar; Kun-Yung Chang; Frank Lambrecht
- Web page: https://patentgrep.com/patent/US10503201B2

## CPC

- G06F 1/08: Clock generators with changeable or programmable clock frequency
- G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators}
- G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C 29/022: {in I/O circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/50012: {of timing}
- H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines}
- H04L 7/0033: {Correction by delay}
- H04L 7/0091: {Transmitter details}
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L 7/10: Arrangements for initial synchronisation
- H04L 25/14: Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver}
- H04L 7/0004: {Initialisation of the receiver (H04L7/0075 and H04L7/10 take precedence)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.

## Claims

### Claim 1

A memory controller comprising:
a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller;
a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount; and
an adjustment circuit to update the sample timing of the data receiver based on the amount of drift.

### Claim 2 (depends on 1)

The memory controller of claim 1, further comprising an interface circuit to establish a setting for the sample timing of the strobe receiver.

### Claim 3 (depends on 2)

The memory controller of claim 2, wherein the amount of the drift is due to a change in condition in an environment of the memory controller.

### Claim 4 (depends on 3)

The memory controller of claim 3, further comprising a circuit to calibrate an initial phase for the sample timing of the data receiver.

### Claim 5 (depends on 1)

The memory controller of claim 1, further comprising:
a transmitter to output write data; and
a circuit to generate a transmit clock signal to time transmission of the write data from the transmitter; and
a circuit to calibrate an initial phase for the transmission of the write data.

### Claim 6 (depends on 1)

The memory controller of claim 1, further comprising a receiver circuit to receive a reference clock, wherein a timing of the reference clock controls at least one of transmitting or receiving data.

### Claim 7 (depends on 6)

The memory controller of claim 6, further comprising at least one mixer to generate a transmit clock signal using the reference clock or generate a receive clock signal using the reference clock.

### Claim 8 (depends on 7)

The memory controller of claim 7, further comprising a calibration circuit to calibrate the transmit clock signal and the receive clock signal.

### Claim 9 (depends on 8)

The memory controller of claim 8, further comprising calibration logic to initiate the calibration.

### Claim 10 (depends on 9)

The memory controller of claim 9, further comprising calibration logic to initiate the calibration as a result of an instruction.

### Claim 11

A method of operation of a memory controller, the method comprising:
receiving a strobe signal, where a phase of the strobe signal has a drift relative to a reference clock by an amount;
sampling data using the strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller; and
updating, based on the amount of the drift, sample timing for the data being sampled by the strobe signal.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
generating a transmit clock signal using the reference clock;
transferring data with the memory device in connection with a data transfer operation; and
calibrating the transmit clock signal and the receive clock signal while the data transfer operation is occurring.

### Claim 13 (depends on 12)

The method of claim 12, wherein the calibration is initiated by an instruction.

### Claim 14 (depends on 12)

The method of claim 12, wherein the calibration is initiated by a change in a condition of a system in which the memory controller operates.

### Claim 15 (depends on 11)

The method of claim 11, further comprising:
generating a set of internal reference clock signals; and
phase mixing the set of internal reference clock signals in response to a control signal to generate a receive clock signal, the receive clock signal to be used in the sampling of the data.

### Claim 16 (depends on 11)

The method of claim 11, further comprising establishing a setting for the sample timing.

### Claim 17 (depends on 11)

The method of claim 11, wherein the amount of drift is due to a change in condition in an environment of the memory controller.

### Claim 18 (depends on 11)

The method of claim 11, further comprising calibrating an initial phase for the sample timing for data to be sampled by the strobe signal.

### Claim 19 (depends on 11)

The method of claim 11, further comprising:
calibrating an initial phase to transmit write data in connection with a write operation;
generating a transmit clock signal to time transmission of the write data; and
outputting the write data in connection with a write operation.

### Claim 20

A memory controller comprising:
means for sampling data using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller;
means for receiving the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount; and
means for updating sample timing of the data based on the amount of the drift.