# US 10,503,196 B2 · Bias generation and distribution for a large array of sensors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,196 B2 - Document ID: US10503196B2 - Status: Granted - Kind: B2 - Application number: 15/958,741 - Filed: 2018-04-20 - Published: 2019-10-24 - Granted: 2019-12-10 - Earliest claimed: 2018-04-20 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Sameer Wadhwa; Yi Wang; Lennart Mathe - Web page: https://patentgrep.com/patent/US10503196B2 ## CPC - G05F 3/262: {using field-effect transistors only} - H03K 3/011: Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature {(to maintain energy constant H03K3/015)} - G05F 3/20: using diode- transistor combinations (G05F3/18 takes precedence) - G05F 3/245: {producing a voltage or current as a predetermined function of the temperature} - G05F 3/247: {producing a voltage or current as a predetermined function of the supply voltage} - G06F 3/0416: {Control or interface arrangements specially adapted for digitisers} - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal. ## Claims ### Claim 1 A bias generation circuit, comprising: a bias voltage generator, including: a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal; a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground; and an array of sensors coupled to the first terminal and the second terminal, wherein each sensor of the array of sensors comprises a local bias replica coupled to the first terminal and the second terminal, and wherein the local bias replica comprises: a local NMOS transistor having a gate of the local NMOS transistor coupled to the first terminal; a local resistor having a first local resistor terminal and a second local resistor terminal, wherein the first local resistor terminal couples to a source of the local NMOS transistor; and a local PMOS transistor having a source of the local PMOS transistor coupled to the second local resistor terminal, a gate of the local PMOS transistor coupled to the second terminal, and a drain of the local PMOS transistor coupled to a local ground. ### Claim 2 (depends on 1) The bias generation circuit of claim 1, wherein the bias voltage generator is configured to generate a first bias voltage at the first terminal and a second bias voltage at the second terminal. ### Claim 3 (depends on 1) The bias generation circuit of claim 1 further comprising a main current mirror coupled to the bias voltage generator, wherein the main current mirror comprises a second main PMOS transistor mirroring a current from a current source, wherein the second main PMOS transistor is configured to have a source of the second main PMOS transistor coupled to a main supply voltage, a gate of the second main PMOS transistor coupled to the current source, and a drain of the second main PMOS transistor coupled to the first terminal. ### Claim 4 (depends on 1) The bias generation circuit of claim 1, wherein each sensor of the array of sensors further comprises a local current mirror mirroring a current of the local bias replica. ### Claim 5 (depends on 4) The bias generation circuit of claim 4, wherein the local current mirror is configured to provide a bias current to a sensing circuit. ### Claim 6 (depends on 4) The bias generation circuit of claim 4, wherein the local current mirror comprises a second local PMOS transistor having a source of the second local PMOS transistor coupled to a local supply voltage and a gate and a drain of the second local PMOS transistor both coupled to a drain of the local NMOS transistor. ### Claim 7 (depends on 1) The bias generation circuit of claim 1, wherein the local ground and the main ground are configured to be electrically coupled through a ground interconnect. ### Claim 8 (depends on 1) The bias generation circuit of claim 1, wherein the local resistor has a resistance value that is about k time a resistance value of the main resistor, wherein k is a positive number. ### Claim 9 (depends on 8) The bias generation circuit of claim 8, wherein the local NMOS transistor and the local PMOS transistor are sized to mirror a current that is substantially 1/k times a current flowing through the bias voltage generator. ### Claim 10 (depends on 9) The bias generation circuit of claim 9, wherein the main NMOS transistor has a same channel length as the local NMOS transistor and wherein the main NMOS transistor has a width that is substantially k times a width of the local NMOS transistor. ### Claim 11 (depends on 9) The bias generation circuit of claim 9, wherein the main PMOS transistor has a same channel length as the local PMOS transistor and wherein the main PMOS transistor has a width that is substantially k times a width of the local PMOS transistor. ### Claim 12 (depends on 1) The bias generation circuit of claim 1, wherein the local bias replica for each sensor of the array of sensors is substantially the same. ### Claim 13 (depends on 1) The bias generation circuit of claim 1, wherein the array of sensors is an array of fingerprint sensors or touch sensors. ### Claim 14 (depends on 1) The bias generation circuit of claim 1, wherein the bias voltage generator is at a periphery of the array of sensors. ### Claim 15 A method, comprising: providing a current source; generating a first bias voltage at a first terminal and a second bias voltage at a second terminal by a bias voltage generator having a main PMOS transistor, a main NMOS transistor, and a main resistor serially coupled, wherein a drain and a gate of the main NMOS transistor both coupled to the first terminal; a first main resistor terminal of the main resistor couples to a source of the main NMOS transistor; and a source of the main PMOS coupled to a second main resistor terminal of the main resistor and a drain and a gate of the main PMOS transistor both coupled to the second terminal, wherein the second terminal couples to a main ground; mirroring a current of the current source to the bias voltage generator; and coupling an array of sensors to the first bias voltage and the second bias voltage, wherein each sensor of the array of sensors comprises a local bias replica coupled to the first terminal and the second terminal, and wherein the local bias replica comprises: a local NMOS transistor having a gate of the local NMOS transistor coupled to the first terminal; a local resistor having a first local resistor terminal and a second local resistor terminal, wherein the first local resistor terminal couples to a source of the local NMOS transistor; and a local PMOS transistor having a source of the local PMOS transistor coupled to the second local resistor terminal, a gate of the local PMOS transistor coupled to the second terminal, and a drain of the local PMOS transistor coupled to a local ground. ### Claim 16 (depends on 15) The method of claim 15, wherein the local ground and the main ground are configured to be electrically coupled through a ground interconnect. ### Claim 17 (depends on 15) The method of claim 15, wherein the local resistor has a resistance value that is k time a resistance value of the main resistor, wherein k is a positive number. ### Claim 18 (depends on 17) The method of claim 17, wherein the main NMOS transistor has a same channel length as the local NMOS transistor and wherein the main NMOS transistor has a width that is substantially k times a width of the local NMOS transistor. ### Claim 19 (depends on 15) The method of claim 15, wherein each sensor of the array of sensors further comprises a local current mirror mirroring a current of the local bias replica. ### Claim 20 (depends on 19) The method of claim 19, wherein the local current mirror is configured to provide a bias current to a sensing circuit. ### Claim 21 (depends on 15) The method of claim 15, wherein the array of sensors is an array of fingerprint sensors or touch sensors.