# US 10,503,186 B2 · Low power ideal diode control circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,503,186 B2 - Document ID: US10503186B2 - Status: Granted - Kind: B2 - Application number: 15/638,892 - Filed: 2017-06-30 - Published: 2017-10-19 - Granted: 2019-12-10 - Earliest claimed: 2014-12-24 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Timothy Bryan Merkin; Hassan Pooya Forghani-Zadeh - Web page: https://patentgrep.com/patent/US10503186B2 ## CPC - G05F 1/575: characterised by the feedback circuit - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract In described examples of a circuit that operates as a low-power ideal diode, and an IC chip that contains the ideal diode circuit, the circuit includes: a first P-channel transistor connected to receive an input voltage on a first terminal and to provide an output voltage on a second terminal; a first amplifier connected to receive the input voltage and the output voltage and to provide a first signal that dynamically biases a gate of the first P-channel transistor as a function of the voltage across the first P-channel transistor; and a second amplifier connected to receive the input voltage and the output voltage and to provide a second signal that acts to turn off the gate of the first P-channel transistor responsive to the input voltage being less than the output voltage. ## Claims ### Claim 1 A circuit comprising: a first P-channel transistor having: a gate; a first terminal coupled to an input node; and a second terminal coupled to an output node; a first amplifier having: a first input coupled to the input node; a second input coupled to the output node; and a first amplifier output, the first amplifier configured to control the first amplifier output responsive to a voltage difference between the first and second inputs of the first amplifier; a second amplifier having: a first input coupled to the input node and having a first input voltage; a second input coupled to the output node and having a second input voltage; and a second amplifier output, the second amplifier configured to control the second amplifier output responsive to whether the first input voltage is lower than the second input voltage; and an output stage having: a first input coupled to the first amplifier output; a second input coupled to the second amplifier output; and an output stage output coupled to the gate of the first P-channel transistor; the output stage configured to: dynamically bias the gate of the first P-channel transistor responsive to the first amplifier output; and turn off the first P-channel transistor responsive to the second amplifier output; the output stage comprising a second P-channel transistor having: a gate; a first terminal coupled to the output stage output; and a second terminal coupled to a ground node; and the first amplifier comprising: a third P-channel transistor having: a gate; a source coupled to the second input of the first amplifier; and a drain coupled through a current source to the ground node; and a fourth P-channel transistor having: a gate coupled to the gate of the third P-channel transistor and to the drain of the third P-channel transistor; a source coupled to the first input of the first amplifier; and a drain coupled to the first amplifier output. ### Claim 2 (depends on 1) The circuit of claim 1, wherein the first amplifier and the second amplifier have overlapping regions of operation. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the circuit is a complementary metal-oxide semiconductor (CMOS) circuit. ### Claim 4 (depends on 2) The circuit of claim 2, wherein a quiescent current in the circuit is less than 1.25 μA. ### Claim 5 (depends on 2) The circuit of claim 2, wherein the circuit is configured to prevent current between the output node and the ground node when the first input voltage is lower than the second input voltage. ### Claim 6 (depends on 1) The circuit of claim 1, wherein the second P-channel transistor is configured to pull the gate of the first P-channel transistor towards a voltage of the ground node responsive to the second P-channel transistor being turned on. ### Claim 7 (depends on 4) The circuit of claim 4, wherein the first amplifier comprises: an N-channel transistor having: a gate coupled to the first amplifier output; a first terminal coupled to the first amplifier output; and a second terminal coupled to the ground node; the third and fourth P-channel transistors together forming an operational transconductance amplifier (OTA) having an output at the drain of the fourth P-channel transistor. ### Claim 8 (depends on 7) The circuit of claim 7, wherein the third P-channel transistor is a floating DC voltage reference. ### Claim 9 (depends on 7) The circuit of claim 7, wherein the second amplifier comprises fifth, sixth and seventh P-channel transistors forming a common-gate amplifier, the fifth P-channel transistor having a source coupled to the input node, and the sixth and seventh P-channel transistors having respective sources coupled to the output node. ### Claim 10 (depends on 9) The circuit of claim 9, wherein the fifth P-channel transistor is a floating DC voltage reference. ### Claim 11 (depends on 9) The circuit of claim 9, wherein: the sixth P-channel transistor has a drain coupled to the output stage output, and the sixth P-channel transistor is configured to pull the gate of the first P-channel transistor towards a voltage of the output node responsive to the sixth P-channel transistor being turned on; and the seventh P-channel transistor has a drain coupled to the gate of the second P-channel transistor, and the seventh P-channel transistor is configured to pull the gate of the second P-channel transistor towards the voltage of the output node responsive to the seventh P-channel transistor being turned on. ### Claim 12 (depends on 11) The circuit of claim 11, wherein the N-channel transistor is a first N-channel transistor, and the output stage comprises: a second N-channel transistor having: a gate coupled to the first amplifier output; a first terminal coupled to the gate of the second P-channel transistor; and a second terminal coupled to the ground node; and a resistor coupled between the output node and the gate of the second P-channel transistor. ### Claim 13 (depends on 12) The circuit of claim 12, wherein the resistor is a first resistor, and the output stage comprises a second resistor coupled between the output node and the gate of the first P-channel transistor. ### Claim 14 (depends on 1) The circuit of claim 1, wherein the circuit is configured to operate as a low-power ideal diode. ### Claim 15 A circuit comprising: a first P-channel transistor having: a gate; a first terminal coupled to an input node; and a second terminal coupled to an output node; a first amplifier having: a first input coupled to the input node; a second input coupled to the output node; and a first amplifier output; a second amplifier having: a first input coupled to the input node; a second input coupled to the output node; and a second amplifier output; and an output stage comprising: a second P-channel transistor having: a first terminal coupled to the gate of the first P-channel transistor; a second terminal coupled to a ground node; and a gate and an N-channel transistor having: a gate coupled to the first amplifier output; a first terminal coupled to the gate of the second P-channel transistor; and a second terminal coupled to the ground node. ### Claim 16 (depends on 15) The circuit of claim 15, wherein the first amplifier comprises: a third P-channel transistor having: a source coupled to the output voltage node; and a drain coupled through a current source to the ground; and a fourth P-channel transistor having a source coupled to the input voltage node; a drain coupled to the first amplifier output; and a gate coupled to a gate of the third P-channel transistor and to the drain of the third P-channel transistor. ### Claim 17 (depends on 16) The circuit of claim 16, wherein the N-channel transistor is a first N-channel transistor, and the first amplifier comprises a second N-channel transistor having: a gate coupled to the first amplifier output; a drain coupled to the first amplifier output; and a source coupled to the ground node. ### Claim 18 (depends on 17) The circuit of claim 17, wherein the current source is a first current source, and the second amplifier comprises fifth, sixth and seventh P-channel transistors having respective gates, sources and drains, and whose gates are coupled to the drain of the fifth P-channel transistor; the drain of the fifth P-channel transistor coupled through a second current source to the ground node, the source of the fifth P-channel transistor coupled to the input node, and the sources of the sixth and seventh P-channel transistors coupled to the output node. ### Claim 19 (depends on 18) The circuit of claim 18, wherein the drain of the sixth P-channel transistor is coupled to the gate of the first P-channel transistor, and the drain of the seventh P-channel transistor is coupled to the gate of the second P-channel transistor. ### Claim 20 (depends on 19) The circuit of claim 19, wherein the output stage comprises a resistor coupled between the output node and the gate of the second P-channel transistor. ### Claim 21 (depends on 20) The circuit of claim 20, wherein the resistor is a first resistor, and the output stage comprises a second resistor coupled between the output node and the gate of the first P-channel transistor. ### Claim 22 (depends on 15) The circuit of claim 15, wherein the circuit is a complementary metal-oxide semiconductor (CMOS) circuit. ### Claim 23 (depends on 15) The circuit of claim 15, wherein a quiescent current in the circuit is less than 1.25 μA. ### Claim 24 (depends on 15) The circuit of claim 15, wherein the circuit is configured to prevent current between the output node and a ground node when the input node has a voltage lower than the output node. ### Claim 25 (depends on 15) The circuit of claim 15, wherein the circuit is configured to operate as a low-power ideal diode. ### Claim 26 (depends on 15) The circuit of claim 15, wherein the first amplifier and the second amplifier have overlapping regions of operation. ### Claim 27 (depends on 15) The circuit of claim 15, wherein the first amplifier output is coupled through the output stage to the gate of the first P-channel transistor, and the first amplifier is configured to dynamically bias the gate of the first P-channel transistor responsive to a voltage difference between the first and second inputs of the first amplifier. ### Claim 28 (depends on 15) The circuit of claim 15, wherein the second amplifier output is coupled through the output stage to the gate of the first P-channel transistor, and the second amplifier is configured to turn off the first P-channel transistor responsive to the input node having a voltage lower than the output node. ### Claim 29 (depends on 15) The circuit of claim 15, wherein the first amplifier output is coupled through the output stage to the gate of the first P-channel transistor, the second amplifier output is coupled through the output stage to the gate of the first P-channel transistor, the first amplifier is configured to dynamically bias the gate of the first P-channel transistor responsive to a voltage difference between the first and second inputs of the first amplifier, and the second amplifier is configured to turn off the first P-channel transistor responsive to the input node having a voltage lower than the output node.