# US 10,502,896 B2 · Method and structure providing optical isolation of a waveguide on a silicon-on-insulator substrate

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- Number: US 10,502,896 B2
- Document ID: US10502896B2
- Status: Granted
- Kind: B2
- Application number: 16/247,996
- Filed: 2019-01-15
- Published: 2019-05-30
- Granted: 2019-12-10
- Earliest claimed: 2012-06-04
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Roy E. Meade
- Web page: https://patentgrep.com/patent/US10502896B2

## CPC

- G02B 6/136: by etching
- G02B 6/122: Basic optical elements, e.g. light-guiding paths
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- G02B 2006/12061: {Silicon}
- H10D 86/01: Manufacture or treatment
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Disclosed are a method and structure providing a silicon-on-insulator substrate on which photonic devices are formed and in which a core material of a waveguide is optically decoupled from a support substrate by a shallow trench isolation region.

## Claims

### Claim 1

A method of forming an integrated structure, the method comprising:
forming a shallow trench isolation region in a first semiconductor substrate;
filing a trench of the shallow trench isolation region with a first dielectric material having a first index of refraction;
forming a waveguide on a second substrate, wherein the second substrate includes a second dielectric material, wherein the waveguide is formed of a semiconductor material over the second dielectric material, and wherein the semiconductor material has a second index of refraction greater than the first index of refraction; and
attaching the second substrate to the first semiconductor substrate, wherein the second dielectric material faces the first substrate and wherein the waveguide is located over the shallow trench isolation region,
wherein the shallow trench isolation region comprises silicon dioxide within the trench.

### Claim 2 (depends on 1)

The method according to claim 1, wherein a combined thickness of the second dielectric material and the shallow trench isolation region is at least 1000 nm.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the first semiconductor substrate and the second substrate each comprises silicon.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the waveguide comprises a core region surrounded by a cladding region, the cladding region being formed at least in part by the second dielectric material.

### Claim 5 (depends on 4)

The method according to claim 4, wherein the core region comprises silicon and the cladding region comprises silicon dioxide.

### Claim 6 (depends on 1)

The method according to claim 1, further comprising an area of the semiconductor material of the second substrate on which an electronic circuit element is formed.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the first semiconductor substrate and the second substrate together form a silicon-on-insulator structure.

### Claim 8 (depends on 1)

The method according to claim 1, further comprising a third dielectric material over the semiconductor material of the second substrate.

### Claim 9 (depends on 8)

The method according to claim 8, wherein the third dielectric material is part of an interlayer dielectric structure.