Test network for a network on a chip and a configuration network

An integrated circuit, comprising:

• a network on a chip (NoC);
• and
• a root device;
• a plurality of switches each comprising a plurality of ports;
• a plurality of endpoints coupled to an ingress port and an egress port of a respective one of the plurality of switches via a bus, wherein the bus starts and terminates at the root device;
• a plurality of devices under test (DUT), each coupled to a respective one of the plurality of endpoints, wherein each of the plurality of endpoints is assigned a respective unique address and is configured to:
• in response to receiving a first address data vector on the bus that contains the unique address, forward first test data received in a first test data vector to a first DUT of the plurality of DUTs and transmit resulting data received from the first DUT to a downstream endpoint using the bus;
• and
• in response to receiving a second address data vector on the bus that does not contain the unique address, forward second test data received in a second test data vector to the downstream endpoint using the bus,
• wherein the first and second address data vectors and the first and second test data vectors each contain respective control bits, wherein the respective control bits are forwarded to the downstream endpoint without being changed.

A method of testing an integrated circuit comprising a plurality of switches each comprising a plurality of ports and a plurality of endpoints coupled to an ingress port and an egress port of a respective one of the plurality of switches via a bus, wherein the bus starts and terminates at a root device, the method comprising:

• receiving, using the bus, a first address data vector at a first endpoint of the plurality of endpoints;
• determining that the first address data vector contains a unique address assigned to the first endpoint;
• forwarding first test data received in a first test data vector to a DUT coupled to the first endpoint, wherein the first address data vector and the first test data vector are in a first packet;
• transmitting, using the bus, resulting data received from the DUT from the first endpoint to a second endpoint of the plurality of endpoints;
• receiving, using the bus, a second address data vector at the first endpoint;
• determining that the second address data vector does not contain the unique address assigned to the first endpoint;
• forwarding, using the bus, second test data received in a second test data vector to the second endpoint, wherein the second address data vector and the second test data vector are in a second packet;
• and
• toggling a logical state of a select signal in the first endpoint based on comparing the unique address to address data in the first and second address data vectors.