# US 10,502,782 B2 · Synthesis for random testability using unreachable states in integrated circuits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,502,782 B2 - Document ID: US10502782B2 - Status: Granted - Kind: B2 - Application number: 15/809,315 - Filed: 2017-11-10 - Published: 2019-05-16 - Granted: 2019-12-10 - Earliest claimed: 2017-11-10 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Victor N. Kravets; Haoxing Ren; Mary P. Kusko; Spencer K. Millican - Web page: https://patentgrep.com/patent/US10502782B2 ## CPC - G01R 31/3177: Testing of logic operation, e.g. by logic analysers - G06F 30/00: Computer-aided design [CAD] - G06F 30/30: Circuit design - G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist - G06F 30/333: Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A system and method for using unreachable states of a circuit design in a testing mode to increase random testability of a random resistant logic circuit. Control-improving logic circuitry is integrated into a logic circuit design to improve its testability and will not affect behavior of the design in its functional mode (by remaining “inactive” in the functional mode of the integrated circuit). The control-improving logic circuitry is automatically activated in testing mode. The control improving logic circuit is generated selectively for random resistant logic circuit regions that exhibit limited controllability in the functional mode and improves controllability of random resistant logic in the testing mode. The improved controllability results from activating test circuitry in the states that are not reachable during normal functionality. The utilization of unreachable states of a design renders unnecessary use of an explicit test enable signal, and provides for more compact implementation of test circuitry. ## Claims ### Claim 1 A method of testing an integrated circuit having a random resistant logic circuit that exhibits limited controllability or observabilty random resistant output signals, said method comprising: providing control-improving logic circuit operatively connected to said random resistant logic circuit; and receiving, at said control-improving logic circuit, input net signals corresponding to unreachable states of said random resistant logic circuit during said functional mode of operation; and activating said control-improving logic circuit responsive to said input net signals in a testing mode of operation to increase controllability of said random resistant output signals, said activated control-improving logic circuit preserving original functionality of said output signals of said random resistant logic circuit responsive to said input net signals in the functional mode, and yielding new output signals of said combinational logic circuit corresponding to said unreachable states for testing said random resistant logic circuit in said testing mode of operation, said unreachable states being a state of said integrated circuit that can be accessed only during the testing mode of said integrated circuit and is not reachable when said integrated circuit is operating in the functional mode. ### Claim 2 (depends on 1) The method of claim 1, wherein said control-improving logic circuit is active during a testing mode of said integrated circuit and remains inactive when said integrated circuit is in its functional mode. ### Claim 3 (depends on 2) The method of claim 2, using existing logic circuitry of said integrated circuit to generate said input net signals for said activating said control-improving logic circuit. ### Claim 4 (depends on 2) The method of claim 2, wherein said integrated circuit is forced into said testing mode of operation without using a test enable signal. ### Claim 5 (depends on 1) The method of claim 1, wherein said random resistant logic circuit lacks “1”-controllability, said control-improving logic circuit including an OR gate for increasing said “1”-controllability of said random resistant logic circuit. ### Claim 6 (depends on 1) The method of claim 1, wherein said random resistant logic circuit lacks “0”-controllability, said control-improving logic circuit including an AND gate for increasing said “0”-controllability of said random resistant logic circuit. ### Claim 7 (depends on 4) The method of claim 4, further comprising: automatically activating said testing mode of operation responsive to receiving said input net signals corresponding to said unreachable states or a subset of said unreachable states at said control-improving logic circuit. ### Claim 8 (depends on 4) The method of claim 4, further comprising: receiving, at a weighting function circuit, plural input net signals corresponding to subsets of unreachable states at each of different circuit paths of said integrated circuit; applying a weight to each of said plural input net signals received for each path; and automatically activating said control-improving logic circuit corresponding to a input net signals of a circuit path based on said applied weight. ### Claim 9 A computer-implemented method of using unreachable states as don't care conditions to change logic of an integrated circuit design, said method comprising: determining, using a hardware processor, from an existing logic circuit design, unreachable states; computing, using the hardware processor, “don't care” values in terms of said unreachable states; propagating, using the hardware processor, said don't care values to a circuit having a local logic gate in a region of said existing logic circuit design having outputs of limited controllability; and modifying, using the hardware processor, said circuit having said local gate to increase its random testability by one of: adding don't care values if said local gate exhibits limited 0-controllability, or subtracting don't care values if said local gate exhibits limited 1-controllability. ### Claim 10 (depends on 9) The computer-implemented method of claim 9, wherein said existing logic circuit design includes a combinational logic circuit for generating net signals, said method further comprising: subtracting from said computed “don't care” values combinational don't care values which are output from combinational logic circuit of the existing design. ### Claim 11 A system of testing an integrated circuit having a random resistant logic circuit that exhibits limited controllability of random resistant output signals in a functional mode of operation, said system comprising: a control-improving logic circuit operatively connected to said random resistant logic circuit; said control-improving logic circuit configured to receive input net signals corresponding to unreachable states of said random resistant logic circuit during said functional mode of operation; and said control-improving logic circuit configured for automatic activation responsive to said input net signals in a testing mode of operation to increase controllability of said random resistant output signals, said activated control-improving logic circuit preserving original functionality of said output signals of said random resistant logic circuit responsive to said input net signals in the functional mode, and yielding new output signals of said combinational logic circuit corresponding to said unreachable states for testing said random resistant logic circuit in said testing mode of operation, said unreachable states being a state of said integrated circuit that can be accessed only during the testing mode of said integrated circuit and is not reachable when said integrated circuit is operating in the functional mode. ### Claim 12 (depends on 11) The system of claim 11, wherein said control-improving logic circuit is active during a testing mode of said integrated circuit and remains inactive when said integrated circuit is in its functional mode. ### Claim 13 (depends on 12) The system of claim 12, wherein said integrated circuit includes existing logic circuitry, said existing logic circuitry generating said input net signals for said automatic activating said control-improving logic circuit. ### Claim 14 (depends on 12) The system of claim 12, wherein said integrated circuit is forced into said testing mode of operation without using a test enable signal. ### Claim 15 (depends on 11) The system of claim 11, wherein said random resistant logic circuit lacks “1”-controllability, said control-improving logic circuit including an OR gate for increasing said “1”-controllability of said random resistant logic circuit. ### Claim 16 (depends on 11) The system of claim 11, wherein said random resistant logic circuit lacks “0”-controllability, said control-improving logic circuit including an AND gate for increasing said “0”-controllability of said random resistant logic circuit. ### Claim 17 (depends on 14) The system of claim 14, wherein said testing mode of operation is automatically activated responsive to receiving said input net signals corresponding to said unreachable states or a subset of said unreachable states at said control-improving logic circuit. ### Claim 18 (depends on 14) The system of claim 14, further comprising: a weighting function circuit operatively connected to receive plural input net signals corresponding to subsets of unreachable states at each of different circuit paths of said integrated circuit, said weighting function circuit configured to apply a weight to each of said plural input net signals received for each path; and said control-improving logic circuit automatically activated corresponding to input net signals of a circuit path based on said applied weight. ### Claim 19 (depends on 14) The system of claim 14, wherein said unreachable states are used as “don't care” conditions to change logic of a circuit design, said system further comprising: a memory, a hardware processor coupled with said memory and configured to perform a method comprising: determining from an existing logic circuit design, said unreachable states; computing “don't care” values in terms of said unreachable states; propagating said don't care values to a circuit having a local logic gate in a region of said existing logic circuit design having outputs of limited controllability; and modifying said circuit having said local gate to increase its random testability by one of: adding don't care values if said local gate exhibits limited 0-controllability, or subtracting don't care values if said local gate exhibits limited 1-controllability. ### Claim 20 (depends on 19) The system of claim 19, wherein said existing logic circuit design includes a combinational logic circuit for generating net signals, said hardware processor further configured to: subtract from said computed “don't care” values one or more combinational don't care values which are output from combinational logic circuit of the existing design.