# US 10,502,781 B2 · Detection circuits, detection method, and electronic systems for I/O output status > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,502,781 B2 - Document ID: US10502781B2 - Status: Granted - Kind: B2 - Application number: 15/874,371 - Filed: 2018-01-18 - Published: 2018-07-19 - Granted: 2019-12-10 - Earliest claimed: 2017-01-18 - Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation - Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation - Inventors: Zhen Ye Guo; Zhen Jiang Su - Web page: https://patentgrep.com/patent/US10502781B2 ## CPC - G01R 31/31715: {Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer} - G01R 31/31703: {Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193)} - G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)} - G01R 31/3177: Testing of logic operation, e.g. by logic analysers - H03K 5/24: the characteristic being amplitude - H03K 17/687: the devices being field-effect transistors - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - H03K 2005/00013: {Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A detection circuit, a detection method, and an electronic system for detecting an I/O output status are provided. The detection circuit includes a comparison-window generating circuit configured to: detect an I/O data signal, generate a first single pulse signal, determining a first-time window, in response to a rising edge of the I/O data signal, and generate a second single pulse signal, determining a second-time window, in response to a falling edge of the I/O data signal. A first comparison circuit is configured to: receive the first single pulse signal, and compare the I/O drive signal with a preset high-level reference signal within the first time window to obtain a first comparison result. The second comparison circuit is configured to: receive the second single pulse signal, and compare the I/O drive signal with a preset low-level reference signal within the second time window to obtain a second comparison result. ## Claims ### Claim 1 A detection circuit for an I/O output status, comprising: a comparison-window generating circuit, configured to: detect an I/O data signal, wherein the I/O data signal is outputted via an I/O interface circuit as an I/O drive signal, generate a first single pulse signal in response to a rising edge of the I/O data signal, the first single pulse signal determining a first-time window and being delayed with respect to the rising edge of the I/O data signal, and generate a second single pulse signal in response to a falling edge of the I/O data signal, the second single pulse signal determining a second-time window and being delayed with respect to the falling edge of the I/O data signal; a first comparison circuit, configured to: receive the first single pulse signal, and compare the I/O drive signal with a preset high-level reference signal within the first time window to obtain a first comparison result; and a second comparison circuit, configured to: receive the second single pulse signal, and compare the I/O drive signal with a preset low-level reference signal within the second time window to obtain a second comparison result, wherein the low level reference signal has an amplitude smaller than the high level reference signal, and the first comparison result and the second comparison result indicate a status of the I/O driving signal. ### Claim 2 (depends on 1) The detection circuit according to claim 1, wherein the comparison-window generating circuit comprises: a first pulse generating circuit, configured to generate the first single pulse signal with an active level of a logic high in response to the rising edge of the I/O data signal, wherein the first single pulse signal is applied to an enable terminal of the first comparison circuit; and a second pulse generation circuit, configured to generate the second single pulse signal with an active level of a logic low in response to the falling edge of the I/O data signal, wherein the second single pulse signal is applied to an enable terminal of the second comparison circuit. ### Claim 3 (depends on 2) The detection circuit according to claim 2, wherein the first pulse generating circuit comprises: a first switch circuit, having a control terminal being turned on in response to the logic low at the control terminal and being turned off in response to the logic high at the control terminal, wherein the control terminal receives the I/O data signal, a first terminal of the first switch circuit receives a supply voltage of the I/O interface circuit, and a second terminal of the first switch circuit is coupled to a first switch node; a second switch circuit, having a control terminal being turned on in response to the logic high at the control terminal and being turned off in response to the logic low at the control terminal, wherein the control terminal receives the first single pulse signal, a first terminal of the second switch circuit is coupled to the first switch node, and a second terminal of the second switch circuit is grounded; a first AND gate, having a first input terminal coupled to the first switch node, a second input terminal receiving the I/O data signal, and an output terminal outputting a first logic signal; and a first delay chain circuit, configured to delay the first logic signal to obtain the first single pulse signal. ### Claim 4 (depends on 3) The detection circuit according to claim 3, wherein the first delay chain circuit comprises even-numbered cascaded inverters. ### Claim 5 (depends on 2) The detection circuit according to claim 2, wherein the second pulse generating circuit comprises: an inverting circuit, configured to invert the I/O data signal; a third switch circuit, having a control terminal being turned on in response to the logic low at the control terminal and being turned off in response to the logic high at the control terminal, wherein the control terminal receives the I/O data signal, a first terminal of the third switch circuit is coupled to receive a supply voltage of the I/O interface circuit, and a second terminal of the third switch circuit is coupled to a second switch node; a fourth switch circuit, having a control terminal being turned on in response to the logic high at the control terminal and being turned off in response to the logic low at the control terminal, wherein the control terminal receives the second single pulse signal, a first terminal of the fourth switch circuit is coupled to the second switch node, and a second terminal of the fourth switch circuit is grounded; a second AND gate, having a first terminal coupled to the second switch node, a second terminal receiving the I/O data signal, and an output terminal outputting a second logic signal; and a second delay chain circuit, configured to delay the second logic signal to obtain the second single pulse signal. ### Claim 6 (depends on 5) The detection circuit according to claim 5, wherein the second delay chain circuit comprises even-numbered cascaded inverters. ### Claim 7 (depends on 1) The detection circuit according to claim 1, wherein the I/O interface circuit comprises an I/O drive circuit, configured to increase a driving capability of the I/O data signal to obtain the I/O drive signal. ### Claim 8 (depends on 1) The detection circuit according to claim 1, further comprising: a first voltage dividing circuit, configured to divide a supply voltage of the I/O interface circuit at a first division ratio to obtain the high-level reference signal. ### Claim 9 (depends on 8) The detection circuit according to claim 8, further comprising: a second voltage dividing circuit, configured to divide the supply voltage of the I/O interface circuit at a second division ratio to obtain the low-level reference signal, the second division ratio being less than the first division ratio. ### Claim 10 An electronic system, comprising: an I/O interface circuit; and a detection circuit for an I/O output status of the I/O interface circuit, the detection circuit comprising: a comparison-window generating circuit, configured to: detect an I/O data signal, wherein the I/O data signal is outputted via the I/O interface circuit as an I/O drive signal, generate a first single pulse signal in response to a rising edge of the I/O data signal, the first single pulse signal determining a first-time window and being delayed with respect to the rising edge of the I/O data signal, and generate a second single pulse signal in response to a falling edge of the I/O data signal, the second single pulse signal determining a second-time window and being delayed with respect to the falling edge of the I/O data signal; a first comparison circuit, configured to: receive the first single pulse signal, and compare the I/O drive signal with a preset high-level reference signal within the first time window to obtain a first comparison result; and a second comparison circuit, configured to: receive the second single pulse signal, and compare the I/O drive signal with a preset low-level reference signal within the second time window to obtain a second comparison result, wherein the low level reference signal has an amplitude smaller than the high level reference signal, and the first comparison result and the second comparison result indicate a status of the I/O driving signal. ### Claim 11 (depends on 10) The system according to claim 10, wherein the comparison-window generating circuit comprises: a first pulse generating circuit, configured to generate the first single pulse signal with an active level of a logic high in response to the rising edge of the I/O data signal, wherein the first single pulse signal is applied to an enable terminal of the first comparison circuit; and a second pulse generation circuit, configured to generate the second single pulse signal with an active level of a logic low in response to the falling edge of the I/O data signal, wherein the second single pulse signal is applied to an enable terminal of the second comparison circuit. ### Claim 12 (depends on 11) The system according to claim 11, wherein the first pulse generating circuit comprises: a first switch circuit, having a control terminal being turned on in response to the logic low at the control terminal and being turned off in response to the logic high at the control terminal, wherein the control terminal receives the I/O data signal, a first terminal of the first switch circuit receives a supply voltage of the I/O interface circuit, and a second terminal of the first switch circuit is coupled to a first switch node; a second switch circuit, having a control terminal being turned on in response to the logic high at the control terminal and being turned off in response to the logic low at the control terminal, wherein the control terminal receives the first single pulse signal, a first terminal of the second switch circuit is coupled to the first switch node, and a second terminal of the second switch circuit is grounded; a first AND gate, having a first input terminal coupled to the first switch node, a second input terminal receiving the I/O data signal, and an output terminal outputting a first logic signal; and a first delay chain circuit, configured to delay the first logic signal to obtain the first single pulse signal. ### Claim 13 (depends on 12) The system according to claim 12, wherein the first delay chain circuit comprises even-numbered cascaded inverters. ### Claim 14 (depends on 11) The system according to claim 11, wherein the second pulse generating circuit comprises: an inverting circuit, configured to invert the I/O data signal; a third switch circuit, having a control terminal being turned on in response to the logic low at the control terminal and being turned off in response to the logic high at the control terminal, wherein the control terminal receives the I/O data signal, a first terminal of the third switch circuit is coupled to receive a supply voltage of the I/O interface circuit, and a second terminal of the third switch circuit is coupled to a second switch node; a fourth switch circuit, having a control terminal being turned on in response to the logic high at the control terminal and being turned off in response to the logic low at the control terminal, wherein the control terminal receives the second single pulse signal, a first terminal of the fourth switch circuit is coupled to the second switch node, and a second terminal of the fourth switch circuit is grounded; a second AND gate, having a first terminal coupled to the second switch node, a second terminal receiving the I/O data signal, and an output terminal outputting a second logic signal; and a second delay chain circuit, configured to delay the second logic signal to obtain the second single pulse signal. ### Claim 15 (depends on 14) The system according to claim 14, wherein the second delay chain circuit comprises even-numbered cascaded inverters. ### Claim 16 A method for detecting an I/O output status, comprising: detecting an I/O data signal, wherein the I/O data signal is outputted via an I/O interface circuit as an I/O drive signal, generating a first single pulse signal in response to a rising edge of the I/O data signal, the first single pulse signal determining a first-time window and being delayed with respect to the rising edge of the I/O data signal, and generating a second single pulse signal in response to a falling edge of the I/O data signal, the second single pulse signal determining a second-time window and being delayed with respect to the falling edge of the I/O data signal; comparing the I/O drive signal with a preset high-level reference signal within the first time window to obtain a first comparison result; and comparing the I/O drive signal with a preset low-level reference signal within the second time window to obtain a second comparison result, wherein the low level reference signal has an amplitude smaller than the high level reference signal, and the first comparison result and the second comparison result indicate a status of the I/O driving signal. ### Claim 17 (depends on 16) The method according to claim 16, further comprising: generating the first single pulse signal with an active level of a logic high in response to the rising edge of the I/O data signal, wherein the first single pulse signal is applied to an enable terminal of the first comparison circuit; and generating the second single pulse signal with an active level of a logic low in response to the falling edge of the I/O data signal, wherein the second single pulse signal is applied to an enable terminal of the second comparison circuit. ### Claim 18 (depends on 16) The method according to claim 16, wherein the I/O interface circuit comprises an I/O drive circuit, configured to increase a driving capability of the I/O data signal to obtain the I/O drive signal. ### Claim 19 (depends on 16) The method according to claim 16, further comprising: dividing a supply voltage of the I/O interface circuit at a first division ratio to obtain the high-level reference signal. ### Claim 20 (depends on 19) The method according to claim 19, further comprising: dividing the supply voltage of the I/O interface circuit at a second division ratio to obtain the low-level reference signal, the second division ratio being less than the first division ratio.