# US 10,502,769 B2 · Digital voltmeter

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- Number: US 10,502,769 B2
- Document ID: US10502769B2
- Status: Granted
- Kind: B2
- Application number: 15/698,289
- Filed: 2017-09-07
- Published: 2019-03-07
- Granted: 2019-12-10
- Earliest claimed: 2017-09-07
- Applicants: Invecas, Inc.
- Inventors: William Loh; Venkata N. S. N. Rao; Prasad Chalasani
- Web page: https://patentgrep.com/patent/US10502769B2

## CPC

- G01R 19/2503: {for measuring voltage only, e.g. digital volt meters (DVM's) (G01R19/2506 - G01R19/257 take precedence)}
- G01R 13/0272: {for sampling}
- G01R 19/155: Indicating the presence of voltage
- G01R 19/255: using analogue/digital converters of the type with counting of pulses during a period of time proportional to voltage or current, delivered by a pulse generator with fixed frequency
- G01R 15/125: {for digital multimeters}
- G01R 19/16576: {comparing DC or AC voltage with one threshold (G01R19/16514, G01R19/16519, G01R19/16528, G01R19/16533 and G01R19/1659 take precedence)}
- G01R 31/2856: {Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A digital voltmeter, where a number of clock pulses for a first ramp voltage to reach an input voltage is determined. Next, a number of clock pulses for a second ramp voltage to reach the input voltage is determined. One of the first and the second ramp voltages having a least number of clock pulses to reach the input voltage is determined. A determination is made for a number of clock pulses for the determined one of the first and the second ramp voltages to reach a reference voltage. A digital code is generated for the input voltage based on the determined number of clock pulses for reaching the reference voltage and the determined least number of clock pulses for reaching the input voltage.

## Claims

### Claim 1

A method for operating a digital voltmeter, comprising the steps of:
determining a number of clock pulses for a first ramp voltage to reach an input voltage;
determining a number of clock pulses for a second ramp voltage to reach the input voltage;
determining one of the first and the second ramp voltages having a least number of clock pulses to reach the input voltage;
determining a number of clock pulses for the determined one of the first and the second ramp voltages to reach a reference voltage; and
generating a digital code for the input voltage based on the determined number of clock pulses for reaching the reference voltage and the determined least number of clock pulses for reaching the input voltage.

### Claim 2 (depends on 1)

The method of claim 1, wherein the reference voltage is a fractional amount of a rail voltage.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first ramp voltage is an upward ramping voltage signal starting from ground and wherein the second ramp voltage is a downward ramping voltage signal starting from a high voltage.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first ramp voltage is a downward ramping voltage signal starting from a high voltage and the second ramp voltage is an upward ramping voltage signal starting from ground.

### Claim 5

A digital voltmeter comprising:
a multiplexer for selecting between an input voltage and a reference voltage;
a down-ramp generator for generating a downward ramping voltage signal;
an up-ramp generator for generating an upward ramping voltage signal;
a track and hold circuit for providing a selected voltage from the multiplexer to the down-ramp generator and the up-ramp generator;
a first comparator;
a second comparator; and
a digital core,
wherein an output of the multiplexer is coupled to an input of the track and hold circuit,
wherein an output of the down-ramp generator and an output of the track and hold circuit are coupled to inputs of the down-ramp comparator,
wherein an output of the up-ramp generator and the output of the track and hold circuit are coupled to inputs of the up-ramp comparator,
wherein an output of the first comparator indicates when the downward ramping voltages signal reaches the selected voltage,
wherein an output of the second comparator indicates when the upward ramping voltage signal reaches the selected voltage, and
wherein the digital core is configured to control the down-ramp generator, the up-ramp generator, the multiplexer, the track and hold circuit, and the first and second comparators.

### Claim 6 (depends on 5)

The digital voltmeter of claim 5, wherein the down-ramp generator and the up-ramp generator are current sources.

### Claim 7 (depends on 5)

The digital voltmeter of claim 5, wherein the first comparator is an NMOS-based comparator.

### Claim 8 (depends on 5)

The digital voltmeter of claim 5, wherein the second comparator is a PMOS-based comparator.

### Claim 9 (depends on 5)

The digital voltmeter of claim 5, wherein the track and hold circuit comprises a storage capacitor and a switch.

### Claim 10 (depends on 5)

The digital voltmeter of claim 5, wherein the digital core is off-chip, and further comprising input/output pins for connecting the off-chip digital core with the down-ramp generator, the up-ramp generator, the multiplexer, for receiving the input voltage and the reference voltage, for outputting outputs of down-ramp generator and the up-ramp generator.

### Claim 11 (depends on 5)

The digital voltmeter of claim 5, wherein the digital core comprises a counter for counting clock pulses based on the outputs of the down-ramp generator and the up-ramp generator, non-transitory logic for operating the down-ramp generator, the up-ramp generator, and the multiplexer, and registers for storing one or more numbers of counted clock pulses.

### Claim 12 (depends on 11)

The digital voltmeter of claim 11, wherein the logic is coupled to control inputs of the down-ramp generator, the up-ramp generator, and the multiplexer, wherein the input voltage and the reference voltage are coupled to inputs of the multiplexer, and wherein the outputs of the down-ramp generator and the up-ramp generator are coupled to the digital core.

### Claim 13

A built-in self-test (“BIST”) device of an integrated circuit (“IC”), comprising:
a digital voltmeter, and
a matrix for coupling one or more nodes of the IC to be sensed by the digital voltmeter for testing,
wherein the digital voltmeter comprises:
a multiplexer for selecting between an input voltage and a reference voltage;
a down-ramp generator for generating a downward ramping voltage signal;
an up-ramp generator for generating an upward ramping voltage signal;
a track and hold circuit for providing a selected voltage from the multiplexer to the down-ramp generator and the up-ramp generator;
a first comparator;
a second comparator; and
a digital core,
wherein an output of the multiplexer is coupled to an input of the track and hold circuit,
wherein an output of the down-ramp generator and an output of the track and hold circuit are coupled to inputs of the down-ramp comparator,
wherein an output of the up-ramp generator and the output of the track and hold circuit are coupled to inputs of the up-ramp comparator,
wherein an output of the first comparator indicates when the downward ramping voltage signal reaches the selected voltage,
wherein an output of the second comparator indicates when the upward ramping voltage signal reaches the selected voltage, and
wherein the digital core is configured to control the down-ramp generator, the up-ramp generator, the multiplexer, the track and hold circuit, and the first and second comparators.

### Claim 14 (depends on 13)

The BIST device of claim 13, wherein the down-ramp generator and the up-ramp generator are current sources.

### Claim 15 (depends on 13)

The BIST device of claim 13, wherein the first comparator is an NMOS-based comparator.

### Claim 16 (depends on 13)

The BIST device of claim 13, wherein the second comparator is a PMOS-based comparator.

### Claim 17 (depends on 13)

The BIST device of claim 13, wherein the track and hold circuit comprises a storage capacitor and a switch.

### Claim 18 (depends on 13)

The BIST device of claim 13, wherein the digital core is off-chip, and further comprising input/output pins for connecting the off-chip core with the down-ramp generator, the up-ramp generator, the multiplexor, for receiving the input voltage the reference voltage, for outputting outputs of down-ramp generator and the up-ramp generator.

### Claim 19 (depends on 13)

A BIST device of claim 13, wherein the digital core comprises a counter for counting clock pulses based on the outputs of the down-ramp generator and the up-ramp generator, non-transitory logic for operating the down-ramp generator, the up-ramp generator, and the multiplexer, and registers for storing one or more numbers of counted clock pulses.

### Claim 20 (depends on 19)

The BIST device of claim 19, wherein the logic is coupled to control inputs of the down-ramp generator, the up-ramp generator, and the multiplexer, wherein the input voltage and the reference voltage are coupled to inputs of the multiplexer, and wherein the outputs of the down-ramp generator and the up-ramp generator are coupled to the digital core.