# US 10,502,768 B2 · Current detection circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,502,768 B2 - Document ID: US10502768B2 - Status: Granted - Kind: B2 - Application number: 16/118,150 - Filed: 2018-08-30 - Published: 2019-08-08 - Granted: 2019-12-10 - Earliest claimed: 2018-02-06 - Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation - Applicants: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation - Inventors: Hiroshi Yoshino - Web page: https://patentgrep.com/patent/US10502768B2 ## CPC - G01R 19/0092: {Measuring current only} - H02P 29/00: Arrangements for regulating or controlling electric motors, appropriate for both AC and DC motors (arrangements for starting electric motors H02P1/00; arrangements for stopping or slowing electric motors H02P3/00; control of motors that can be connected to two or more different electric power supplies H02P4/00; regulating or controlling the speed or torque of two or more electric motors H02P5/00; vector control H02P21/00) - H03F 3/2173: {of the bridge type} - H03F 3/45183: {Long tailed pairs (H03F3/4521, H03F3/45237 take precedence)} - H03F 2200/126: A diode being coupled in a feedback path of an amplifier stage, e.g. active or passive diode - H03F 2200/129: there being a feedback over the complete amplifier - H03F 2200/156: One or more switches are realised in the feedback circuit of the amplifier stage - H03F 2200/267: A capacitor based passive circuit, e.g. filter, being used in an amplifying circuit - H03F 2200/301: the loading circuit of an amplifying stage comprising a coil - H03F 2200/351: Pulse width modulation being used in an amplifying circuit - H03F 2200/366: Multiple MOSFETs are coupled in parallel - H03F 2200/456: A scaled replica of a transistor being present in an amplifier - H03F 2200/462: the current being sensed - H03F 2203/45116: Feedback coupled to the input of the differential amplifier - H03F 2203/45512: the FBC comprising one or more capacitors, not being switched capacitors, and being coupled between the LC and the IC - H03F 2203/45518: the FBC comprising one or more diodes and being coupled between the LC and the IC - H03F 2203/45534: the FBC comprising multiple switches and being coupled between the LC and the IC - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H02P: CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS - H03F: AMPLIFIERS ## Abstract A current detection circuit has a differential amplification circuit that outputs a differential output current dependent on a voltage difference between input terminals and first and second feedback circuits that output a detection current in response to the differential output current and form a feedback path to each input terminal of the differential amplification circuit. First and second MOS transistors that generate voltages dependent on respective source-drain voltages at a time when drain currents in a forward direction and a backward direction flow through an output MOS transistor are connected to respective input terminals of the differential amplification circuit. ## Claims ### Claim 1 A current detection circuit, comprising: a differential amplification circuit that includes first and second input terminals and outputs first and second differential output currents dependent on a voltage difference between the first and second input terminals; a first feedback circuit that outputs a first detection current in response to the first differential output current and forms a path to the second input terminal; a second feedback circuit that outputs a second detection current in response to the second differential output current and forms a path to the first input terminal; a first MOS transistor that generates, in a state where a drain current in a forward direction flows through an output MOS transistor that supplies an output current to a load, a voltage dependent on a source-drain voltage of the output MOS transistor, between a source of the output MOS transistor and the second input terminal; and a second MOS transistor that generates, in a state where a drain current in a backward direction flows through the output MOS transistor, a voltage dependent on a source-drain voltage of the output MOS transistor, between a drain of the output MOS transistor and the first input terminal. ### Claim 2 (depends on 1) The current detection circuit according to claim 1, wherein the first and second MOS transistors flow a drain current that is 1/N times a drain current of the output MOS transistor, where N is an arbitrary positive number that is greater than 1. ### Claim 3 (depends on 1) The current detection circuit according to claim 1, wherein the first and second MOS transistors have a reduced size with respect to that of the output MOS transistor. ### Claim 4 (depends on 1) The current detection circuit according to claim 1, wherein: the first feedback circuit includes a third MOS transistor that has a source that is connected to the second input terminal and a drain that outputs the first detection current; and the second feedback circuit includes a fourth MOS transistor that has a source that is connected to the first input terminal and a drain that outputs the second detection current. ### Claim 5 (depends on 4) The current detection circuit according to claim 4, comprising: a fifth MOS transistor with a source-drain path that is connected between a gate and a source of the third MOS transistor; and a sixth MOS transistor with a source-drain path that is connected between a gate and a source of the fourth MOS transistor. ### Claim 6 (depends on 5) The current detection circuit according to claim 5, comprising: a diode-connected seventh MOS transistor that is connected to a source-drain path of the fifth MOS transistor in series; and a diode-connected eighth MOS transistor that is connected to a source-drain path of the sixth MOS transistor in series. ### Claim 7 (depends on 1) The current detection circuit according to claim 1, wherein the output MOS transistor supplies a current to an exciting coil of a motor. ### Claim 8 A current detection circuit, comprising: a first MOS transistor that supplies an output current to a load; a second MOS transistor that supplies an output current to the load; a differential amplification circuit that has first and second input terminals and outputs a differential output current dependent on a voltage difference between the first and second input terminals; a third MOS transistor with a source that is connected to sources of the first and second MOS transistors and a drain that is connected to the second input terminal; a fourth MOS transistor that connects a drain of the first MOS transistor to the first input terminal when the first MOS transistor is turned on; a fifth MOS transistor that connects a drain of the second MOS transistor to the first input terminal when the second MOS transistor is turned on; a first feedback circuit that outputs a first detection current in response to a differential output current at a time when the first MOS transistor is turned on and forms a path to the second input terminal; and a second feedback circuit that outputs a second detection current in response to the differential output current at a time when the second MOS transistor is turned on and forms a path to the first input terminal. ### Claim 9 (depends on 8) The current detection circuit according to claim 8, wherein the third MOS transistor flows a drain current that is 1/N times drain currents of the first MOS transistor and the second MOS transistor, where N is an arbitrary positive number that is greater than 1. ### Claim 10 (depends on 8) The current detection circuit according to claim 8, wherein the third MOS transistor has a reduced size with respect to those of the first MOS transistor and the second MOS transistor. ### Claim 11 (depends on 8) The current detection circuit according to claim 8, wherein the load is an exciting coil of a motor. ### Claim 12 (depends on 10) The current detection circuit according to claim 10, wherein: the first feedback circuit includes a sixth MOS transistor that has a source that is connected to the second input terminal and a drain that outputs the first detection current; and the second feedback circuit includes a seventh MOS transistor that has a source that is connected to the first input terminal and a drain that outputs the second detection current. ### Claim 13 (depends on 12) The current detection circuit according to claim 12, comprising: a eighth MOS transistor with a source-drain path that is connected between a gate and a source of the sixth MOS transistor; and a ninth MOS transistor with a source-drain path that is connected between a gate and a source of the seventh MOS transistor. ### Claim 14 (depends on 13) The current detection circuit according to claim 13, comprising: a diode-connected tenth MOS transistor that is connected to a source-drain path of the eighth MOS transistor in series; and a diode-connected eleventh MOS transistor that is connected to a source-drain path of the ninth MOS transistor in series. ### Claim 15 A current detection circuit, comprising: a first MOS transistor with a drain that is connected to a first terminal of an exciting coil of a motor; a second MOS transistor with a drain that is connected to a second terminal of the exciting coil; a differential amplification circuit that has first and second input terminals and outputs a differential output current dependent on a voltage difference between the first and second input terminals; a third MOS transistor with a source that is connected to sources of the first and second MOS transistors and a drain that is connected to the second input terminal; a fourth MOS transistor that connects a drain of the first MOS transistor to the first input terminal when the first MOS transistor is turned on; a fifth MOS transistor that connects a drain of the second MOS transistor to the first input terminal when the second MOS transistor is turned on; a first feedback circuit that outputs a first detection current in response to the differential output current at a time when the first MOS transistor is turned on and forms a path to the second input terminal; and a second feedback circuit that outputs a second detection current in response to the differential output current at a time when the second MOS transistor is turned on and forms a path to the first input terminal. ### Claim 16 (depends on 15) The current detection circuit according to claim 15, wherein the third MOS transistor flows a drain current that is 1/N times drain currents of the first MOS transistor and the second MOS transistor, where N is an arbitrary positive number that is greater than 1. ### Claim 17 (depends on 15) The current detection circuit according to claim 15, wherein the third MOS transistor has a reduced size with respect to those of the first MOS transistor and the second MOS transistor. ### Claim 18 (depends on 15) The current detection circuit according to claim 15, wherein: the first feedback circuit includes a sixth MOS transistor that has a source that is connected to the second input terminal and a drain that outputs the first detection current; and the second feedback circuit includes a seventh MOS transistor that has a source that is connected to the first input terminal and a drain that outputs the second detection current. ### Claim 19 (depends on 18) The current detection circuit according to claim 18, comprising: a eighth MOS transistor with a source-drain path that is connected between a gate and a source of the sixth MOS transistor; and a ninth MOS transistor with a source-drain path that is connected between a gate and a source of the seventh MOS transistor. ### Claim 20 (depends on 19) The current detection circuit according to claim 19, comprising: a diode-connected tenth MOS transistor that is connected to a source-drain path of the eighth MOS transistor in series; and a diode-connected eleventh MOS transistor that is connected to a source-drain path of the ninth MOS transistor in series.