# US 10,502,706 B2 · Direct sensing BioFETs and methods of manufacture

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- Number: US 10,502,706 B2
- Document ID: US10502706B2
- Status: Granted
- Kind: B2
- Application number: 14/810,255
- Filed: 2015-07-27
- Published: 2015-11-19
- Granted: 2019-12-10
- Earliest claimed: 2012-09-08
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yi-Hsien Chang; Chun-Ren Cheng; Shih-Wei Lin; Yi-Shao Liu
- Web page: https://patentgrep.com/patent/US10502706B2

## CPC

- G01N 27/4145: {specially adapted for biomolecules, e.g. gate electrode with immobilised receptors}
- H10D 64/0113: {the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10K 19/10: comprising field-effect transistors
- H10P 50/266: {by vapour etching only}
- H10P 50/283: {by chemical means}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a biological field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a plurality of micro wells having a sensing gate bottom and a number of stacked well portions. A bottom surface area of a well portion is different from a top surface area of a well portion directly below. The micro wells are formed by multiple etching operations through different materials, including a sacrificial plug, to expose the sensing gate without plasma induced damage.

## Claims

### Claim 1

A method of making a BioFET device, comprising:
forming a plurality of FETs on a semiconductor substrate, wherein the plurality of FETs includes respective gate structures formed on respective first surfaces of the semiconductor substrate and respective channel regions;
forming respective sacrificial plugs over respective portions of the respective gate structures for a subset of the plurality of FETs;
forming respective contacts over respective ones of the plurality of FETs and forming a single multi-layer interconnect (MLI) directly over all the plurality of FETs;
etching the MLI to expose at least respective portions of the respective sacrificial plugs, thereby forming respective first well portions of respective micro wells, wherein the respective micro wells each includes a plurality of stacked well portions, wherein the respective micro wells extend over respective channel regions of respective ones of the plurality of FETs; and,
removing the respective sacrificial plugs using a non-plasma etch, thereby forming respective second well portions of the respective micro wells, wherein the respective channel regions extend under the respective micro wells.

### Claim 2 (depends on 1)

The method of claim 1, wherein the gate respective structures includes respective gate electrodes and further comprising:
removing respective portions of the respective gate electrodes of the subset of the plurality of FETs using a non-plasma etch to form respective third well portions of the micro wells.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
removing respective portions of respective gate dielectrics at respective bottoms of the respective micro wells and
depositing silicon nitride, hafnium oxide, or tantalum oxide on the respective bottoms of the respective micro wells.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
coating sidewalls of the respective micro wells with a first coating; and
coating respective bottoms of the respective micro wells with a second coating different from the first coating.

### Claim 5 (depends on 1)

The method of claim 1, wherein forming respective sacrificial plugs comprises:
depositing a protective layer over the respective gate structures;
depositing an inter-layer dielectric (ILD) over the plurality of FETs;
etching openings through the ILD to expose the protective layer for a subset of the plurality of FETs;
soft landing etching the protective layer;
depositing polysilicon to form the respective sacrificial plugs in the openings; and,
planarizing to remove excess polysilicon.

### Claim 6 (depends on 1)

The method of claim 1, wherein removing the respective sacrificial plugs comprises:
etching the respective sacrificial plugs using XeF2; and
removing a dielectric layer below the respective sacrificial plugs by soft etch or wet etch.

### Claim 7 (depends on 1)

The method of claim 1, wherein at least one of the respective micro wells includes a first ridge aligned with a first layer of the MLI.

### Claim 8 (depends on 7)

The method of claim 7, further comprising forming respective gate spacers on respective sidewalls of the respective gate structures, wherein the at least one of the respective micro wells includes a second ridge aligned with an outer edge of the gate spacer.

### Claim 9

A method of making a BioFET device, comprising:
forming a FET on a semiconductor substrate, wherein the FETs includes a gate structure, a channel region, and a source region formed at a first surface of the semiconductor substrate;
forming a sacrificial plug over the gate structure, wherein forming the sacrificial plug includes depositing a dielectric layer over the gate structure, patterning the dielectric layer to include an opening exposing the gate structure, and filling the opening with sacrificial material;
forming a contact and a multi-layer interconnect (MLI) directly over the FET;
etching the MLI to expose at portions of the sacrificial plug, thereby forming a first well portion of a micro well, wherein the micro well includes a plurality of stacked well portions, wherein the micro well extends over the channel region of the FET; and
removing the sacrificial plug, thereby forming a second well portion of the micro well, wherein the channel region extends under the micro well.

### Claim 10 (depends on 9)

The method of claim 9, further including:
forming a second FET on the semiconductor substrate, wherein the second FET includes a second gate structure, a second channel region, and a second source region formed at the first surface of the semiconductor substrate;
forming a dielectric layer over the FET and the second FET and removing a portion of the dielectric layer to expose the gate structure, while leaving the second gate structure covered by the dielectric layer; and
forming a contact to the second gate structure and simultaneously forming a contact to source region and a contact to the second source region.

### Claim 11 (depends on 10)

The method of claim 10, further comprising forming a protective layer over the FET prior to forming the dielectric layer over the FET.

### Claim 12 (depends on 11)

The method of claim 11, wherein the step of removing a portion of the dielectric layer to expose the gate structure includes a first etch step to remove the dielectric layer and a second etch step to remove the protective layer.

### Claim 13 (depends on 10)

The method of claim 10, further including:
forming a spacer along a sidewall of the gate structure; and
wherein removing a portion of the dielectric layer to expose the gate structure further includes exposing the spacer.

### Claim 14 (depends on 9)

The method of claim 9, wherein the gate structure includes a gate electrode and further comprising removing a portion of the gate electrode using a non-plasma etch after removing the sacrificial plug.

### Claim 15 (depends on 14)

The method of claim 14, wherein the gate structure includes a gate dielectric, and further comprising:
removing a portion of the gate dielectric at a bottom of the micro well; and
depositing on the bottom of the micro well, a material selected from the group consisting of silicon nitride, hafnium oxide, and tantalum oxide.

### Claim 16 (depends on 9)

The method of claim 9, further comprising:
coating sidewalls of the micro well with a first coating; and
coating a bottom of the micro well with a second coating.

### Claim 17

A method of forming a BioFET device comprising:
simultaneously forming a first FET device and a second FET device;
forming a dielectric layer over the first FET device and the second FET device;
patterning the dielectric layer to expose a gate structure of the first FET device while leaving unexposed a gate structure of the second FET device;
after patterning the dielectric layer, forming a sacrificial plug contacting the a gate structure of the first FET device;
patterning the dielectric layer a second time to expose a gate structure of the second FET device, a source region of the second FET device, a drain region of the second FET device, a source region of the first FET device, and a drain region of the second FET device;
forming a multi-layer interconnect (MLI) over the first FET device and the second FET device;
removing portions of the MLI and the dielectric layer overlying a channel region of the first FET device and removing the sacrificial plug to form a micro well, the micro well having sidewalls; and
lining the sidewalls of the micro well with a first coating.

### Claim 18 (depends on 17)

The method of claim 17, further comprising removing the respective sacrificial plugs using a non-plasma etch.

### Claim 19 (depends on 17)

The method of claim 17, further comprising removing the gate structure of the first FET device after removing the sacrificial plug.

### Claim 20 (depends on 17)

The method of claim 17 further comprising forming a sidewall spacer on the gate structure of the first FET device, wherein the step of removing portions of the MLI and the dielectric layer overlying a channel region of the first FET device and removing the sacrificial plug to form a micro well includes exposing the sidewall spacer.