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US 10,496,855 B2Granted
Analog sub-matrix computing from input matrixes
AssigneeHewlett Packard Enterprise Development LP
InventorsNaveen Muralimanohar, Ben Feinberg
Life of this patent
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Abstract
A circuit includes an engine to compute analog multiplication results between vectors of a sub-matrix. An analog to digital converter (ADC) generates a digital value for the analog multiplication results computed by the engine. A shifter shifts the digital value of analog multiplication results a predetermined number of bits to generate a shifted result. An adder adds the shifted result to the digital value of a second multiplication result to generate a combined multiplication result.
Claims15
A circuit, comprising:
- an engine formed from a memristor array to compute analog multiplication results between vectors of a sub-matrix, the sub-matrix is programmed from a portion of an input matrix;
- an analog to digital converter (ADC) to generate a digital value for the analog multiplication results computed by the engine;
- a shifter to shift the digital value of analog multiplication result a predetermined number of bits to generate a shifted result;
- and
- an adder to add the shifted result to the digital value of a second multiplication result to generate a combined multiplication result.
2 more elements
A circuit, comprising:
- a first cluster to compute a first intermediate result by multiplying vectors from a first portion of an input matrix;
- a second cluster to compute a second intermediate result by multiplying vectors from a second portion of the input matrix;
- an analog to digital converter (ADC) to digitize the first and second intermediate results, respectively;
- and
- a controller to combine the digitized results of the first and second intermediate results, respectively, wherein each of the first and second clusters include:
- a plurality of engines formed from a memristor array to compute analog multiplication results between vectors of a sub-matrix, the sub-matrix is programmed from a portion of the input matrix;
- a shifter to shift a digital value of a first cluster analog multiplication result a predetermined number of bits to generate a shifted cluster result;
- and
- an adder to add the shifted cluster result to a digital value of a second cluster multiplication result to generate a combined multiplication result from the first cluster and the second cluster.
6 more elements
A method, comprising:
- computing a first analog multiplication result between vectors of a first sub-matrix, the first sub-matrix is programmed from a portion of an input matrix;
- computing a second analog multiplication result between vectors of a second sub-matrix, the second sub-matrix is programmed from another portion of the input matrix;
- generating a digital value for the first and second analog multiplication results, respectively;
- shifting the digital value of first analog multiplication result a predetermined number of bits to generate a shifted result;
- and
- adding the shifted result to the digital value of the second multiplication result to generate a combined multiplication result from the first sub-matrix and the second sub-matrix.
3 more elements
Dependencies are inferred from the claim text.