Network logic synthesis
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
InventorsChi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong Chiang
Life of this patent
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Abstract
A system comprises at least one processor configured to perform technology mapping to map logic elements in a logic netlist to corresponding dual-rail modules in a library. The technology mapping results in a network of interconnected nodes and the mapped dual-rail modules are arranged at corresponding nodes of the network. The processor is configured to optimize the network and perform the technology mapping based on at least one satisfiability-don't-care condition. Performance analysis may be performed by calculating a cycle time of a pipeline node in the network based on a calculated pre-charging finish time and an evaluation finish time of a fanin node of the pipeline node.
Claims20
A system, comprising at least one processor configured to perform:
- technology mapping to map logic elements in a logic netlist to corresponding dual-rail modules in a library, the technology mapping resulting in a network of interconnected nodes, the mapped dual-rail modules arranged at the corresponding nodes of the network;
- a performance analysis to estimate time delays in the network;
- and
- an optimization of the network based on a result of the performance analysis,
- wherein the at least one processor is configured to perform the technology mapping based on at least one satisfiability-don't-care (SDC) condition.
A system comprising at least one processor configured to:
- map logic elements in a logic netlist to corresponding dual-rail modules in a library, the mapping of the logic elements resulting in a network of interconnected nodes and dual-rail modules arranged at corresponding nodes of the networks;
- conduct a performance analysis to estimate time delays in the network;
- optimize the network based on a result of the performance analysis;
- and
- slack match a pipeline in the optimized network.
A system, comprising at least one processor configured to perform:
- technology mapping to map logic elements in a logic netlist to corresponding dual-rail modules in a library, the technology mapping resulting in a network of interconnected nodes, the mapped dual-rail modules arranged at the corresponding nodes of the network;
- and
- an optimization of the network;
- and
- wherein the at least one processor being configured to perform the technology mapping includes being configured to:
- identify a non-critical node among the nodes in the pipeline, based on the calculated cycle times of the nodes in the pipeline;
- and
- replace the dual-rail module at the non-critical node with another dual-rail module from the library, the another dual-rail module having a smaller area than the dual-rail module being replaced, the replacing resulting in no violation of a timing constraint on the overall cycle time of the pipeline.
Dependencies are inferred from the claim text.