Inter-processor communication method for access latency between system-in-package (SIP) dies

A method comprising:

• on a first semiconductor die, receiving first processor bus transactions via a first processor bus;
• on the first semiconductor die, converting the first bus transactions into die-to-die message packets to be communicated to a second semiconductor die via a die-to-die interconnect;
• on the first semiconductor die, utilizing a multiple simultaneous outstanding transaction capability supporting multiple simultaneous outstanding write transactions concurrent with multiple simultaneous outstanding read transactions;
• on the second semiconductor die, transmitting to the first semiconductor die process bus flow control information and elasticity buffer status information pertaining to an elasticity buffer on the second semiconductor die for flow control, the first semiconductor die and the second semiconductor die contained in a common integrated circuit (IC) package;
• classifying processor bus interface messages communicating processor bus interface protocol information and elasticity buffer flow control information according to a first message classification;
• and
• classifying non-processor-bus-interface messages communicating elasticity buffer flow control information according to a second message classification.

Apparatus comprising:

• a common integrated circuit (IC) package;
• a first processor on a first semiconductor die, the first semiconductor die contained in the common IC package;
• a second processor on a second semiconductor die, the second semiconductor die contained in the common IC package;
• first connectivity circuitry on the first semiconductor die, the first connectivity circuitry connected to the first processor via a first processor bus, the first connectivity circuitry configured to convert first processor bus transactions on the first processor bus into die-to-die message packets for communication via a die-to-die interconnect, the first connectivity circuitry further configured to utilize a multiple simultaneous outstanding transaction capability supporting multiple simultaneous outstanding write transactions concurrent with multiple simultaneous outstanding read transactions;
• second connectivity circuitry on the second semiconductor die, the second connectivity circuitry connected to the die-to-die interconnect for receiving the die-to-die message packets, the second connectivity circuitry connected to the second processor via a second processor bus, the second connectivity circuitry configured to convert the die-to-die message packets into second processor bus transactions on the second processor bus, the second connectivity circuitry further configured to provide processor bus flow control information and elasticity buffer status information pertaining to an elasticity buffer in the second connectivity circuitry to the first connectivity circuitry for flow control,
• wherein two message classifications are used for the flow control, the two message classifications comprising:
• a first message classification for processor bus interface messages communicating processor bus interface protocol information and elasticity buffer flow control information;
• and
• a second message classification for non-processor-bus-interface messages communicating elasticity buffer flow control information.